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Common Challenges when Designing IoT PCBs – And How to Solve Them with Cadence
While IoT devices may seem simple to the end users (which is good), the electrical design complexity of these devices is often very high. Designers are required to work with limited board space while functionality and speed requirements continue to increase. These tight spaces, combined with the required highspeed signaling, leads to increased susceptibility to… Common Challenges when Designing IoT PCBs – And How to Solve Them with Cadence
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IP Based Digital Design Management that Goes Beyond the Basics
oin us on Thursday, September 30th to learn why common design management capabilities are not enough and what next generation capabilities are needed for IP based digital design management. Register Today! Here’s what you can learn: Complete digital design management checklist Tagging, branching, and merging Project BOM and IP conflicts Logistics: The webinar will be… IP Based Digital Design Management that Goes Beyond the Basics
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Avoiding SoC Security Threats – What Verification Engineers Should Know
Thursday, September 30, 2021 | 11:00 -11:30 a.m. PDT The development of secure systems is of paramount importance in this age of software intensive electronic systems. Security weaknesses in the SoC hardware can lead to vulnerabilities that may be exploited later on by malicious software. These challenging problems must be addressed pre-silicon and require rigorous… Avoiding SoC Security Threats – What Verification Engineers Should Know
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Scalable HPC platform and memory expansion techniques using Die-to-Die and LPDDR subsystems
With advanced packaging and interface solutions, it is possible to connect multiple CPU clusters (near or far) and share external memory resources among them. We will review some of the IPs required to build such a platform and recommend applications that can benefit from it. This webinar will be useful to designers, architects, and application… Scalable HPC platform and memory expansion techniques using Die-to-Die and LPDDR subsystems
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Digital Design Technology Symposium
A Must-Attend Event HPC, 5G, AI, Automotive: market segments like these are presenting new challenges to ASIC and SoC designers. Synopsys is focused on delivering a continuous stream of innovative solutions with future-proof technologies to address issues such as greater energy efficiency, improved power-performance-area, faster time to market, functional safety, security, and yield optimization. The… Digital Design Technology Symposium
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DesignCon Digital
This online event from the producers of DesignCon features an education program with on-demand webinars presented by a standout speaker list, suppliers with easy-to-find products and services, and multiple matchmaking and networking opportunities – with the quality you’ve come to expect from a DesignCon event. All of our DesignCon Digital education and information presented will… DesignCon Digital
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Thermal Analysis for MMIC and RF PCB Power Applications
Overview The Cadence® Celsius™ Thermal Solver is now integrated with the Cadence AWR Design Environment® V16 platform, supporting electrothermal analysis for MMIC/RFIC, PCB, and module designs. Thermal analysis provides RF circuit designers with insight regarding operating temperatures that can degrade performance and threaten device reliability. This webinar will highlight how the Celsius Thermal Solver uses design… Thermal Analysis for MMIC and RF PCB Power Applications
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Samsung Foundry Forum 2021
Join now and become a member of the Samsung Foundry Forum 2021! Samsung Foundry would like to invite global customers and partners to the Samsung Foundry Forum 2021, designed to share Samsung Foundry's vision, trends, the latest technologies and solutions for various applications in order to strengthen our valuable partnerships.
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Keeping Latency to a Minimum with 400G/800G Ethernet IP
A large volume of data is required for high performance computing (HPC) workloads in data centers. As a result, enabling data processing between machines and servers across long reach channels at high rates becomes mandatory. SoCs for HPC applications such as data center, networking and AI, must support high throughput and minimum latency with maximum… Keeping Latency to a Minimum with 400G/800G Ethernet IP
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Addressing Growing Security Challenges with JasperGold
Join Cadence® Training and Product Engineering Architect Joerg Mueller and Senior Application Engineer Tom Weiss for this free technical training webinar. As a chip designer, you’re probably spending as much headspace on security threats as you are on traditional challenges like power, speed, and functionality. Recent microarchitectural vulnerabilities like “Meltdown” and “Row Hammer” that expose… Addressing Growing Security Challenges with JasperGold
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Benefits of a Common Methodology for Emulation and Prototyping
Many design teams have used some form of hardware verification throughout their verification cycle for years now. Some engineering teams prefer to use emulation, some prefer to use prototyping, and some even use both. Why would engineering teams invest in both platforms? Join our experts to understand why you should consider bridging emulation and prototyping… Benefits of a Common Methodology for Emulation and Prototyping
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UVM for FPGAs (Part 4): IEEE 1800.2 UVM Updates
Abstract: Started with an early adaptor release as Accellera 1.0a, UVM has evolved into few significant versions including UVM 1.1 and UVM 1.2. As with many popular useful standards, UVM has attained the coveted IEEE standardization in 2017. Interestingly, UVM is the first verification methodology to be standardized, and the current version is IEEE 1800.2-2020.… UVM for FPGAs (Part 4): IEEE 1800.2 UVM Updates
12 events found.