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DFT for chiplets & 3D ICs using Tessent Multi-die
3D IC (2.5D/3D) designs are on the rise. Design for Test (DFT) for chiplets must be general purpose so they can be tested stand alone and easy to test after assembly into 2.5D or 3D devices. In this webinar you will learn how to use Tessent Multi-die and still adhere to standards like IEEE 1149.1,… DFT for chiplets & 3D ICs using Tessent Multi-die
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CXL DevCon 2024
Santa Clara Marriott 2700 Mission College Blvd, Santa Clara, CA, United StatesThe CXL Consortium is looking forward to hosting the first Compute Express Link® (CXL®) DevCon from April 30 – May 1, 2024, in Santa Clara, California! CXL DevCon is a unique opportunity for our Members to learn directly from CXL technology experts. Attendees will participate in CXL technical training, view available products and technology demonstrations,… CXL DevCon 2024
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TSMC 2024 Technology Workshop – Austin
JW Marriott Austin 110 E 2nd St, Austin, TX, United States08:30 – 09:30 Registration & Partner Pavilion 09:30 – 09:40 Welcome & Opening Remarks 09:40 – 10:00 Market Outlook – Powering AI Together 10:00 – 10:30 Advanced Technology Leadership 10:30 – 11:00 Coffee Break & Ecosystem Pavilion 11:00 – 11:25 Specialty Technology Leadership 11:25 – 11:50 Manufacturing Excellence 11:50 – 13:00 Lunch & Ecosystem Pavilion… TSMC 2024 Technology Workshop – Austin
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Smart methods for DFT chip architecture & validation
Combining market-leading design-for-test (DFT) technologies with best-in-class netlist synthesis allows you to achieve DFT success more quickly. Many customers, including those for emulation and IC test, have challenges with scaling architectures. This webinar describes how Siemens emulation and silicon test solutions can work together to provide a smart DFT plug-and-play architecture for Veloce ICs. The… Smart methods for DFT chip architecture & validation
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Keysight EDA Connect Tour – Austin
Topgolf Austin 2700 Esperanza Crossing, Austin, TX, United StatesKeysight is excited to announce the next destination stops of our EDA Connect World Tour: Austin, TX and Burlington, MA. Save the dates for our upcoming events in Austin, TX on May 2 or Burlington, MA on May 16, where we'll explore the future of AI in 6G to 3D Module integration. These technical sessions promise to recharge your… Keysight EDA Connect Tour – Austin
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ChipEx 2024
Tel Aviv Convention Center Rokach Boulevard 101, Tel Aviv, IsraelChipEx2024, the largest annual event of the Israeli semiconductor industry, will be held on May 7-8, 2024 in Tel Aviv, Israel. ChipEx2024 showcases companies including manufacturers, developers and suppliers of advanced hardware technologies & services. It also includes a technical seminar where the world's leading experts address the industry's most relevant issues. The event is… ChipEx 2024
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User2User Europe 2024
Hilton Munich Airport Terminalstraße Mitte 20, 85356 München-Flughafen, Munich, GermanyUser2User is the perfect opportunity to learn, share and network with fellow technical experts who design leading-edge products using Siemens EDA tools. Dedicated to end-users of Siemens EDA solutions, this conference is free to attend and includes innovative keynotes from industry leaders, enriching technical sessions as well as a chance to network with colleagues and… User2User Europe 2024
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TSMC Technology Workshop 2024 – Boston
Boston Marriott Burlington One Burlington Mall Road, Burlington, MA, United States08:30 – 09:30 Registration & Partner Pavilion 09:30 – 09:40 Welcome & Opening Remarks 09:40 – 10:00 Market Outlook – Powering AI Together 10:00 – 10:30 Advanced Technology Leadership 10:30 – 11:00 Coffee Break & Ecosystem Pavilion 11:00 – 11:25 Specialty Technology Leadership 11:25 – 11:50 Manufacturing Excellence 11:50 – 13:00 Lunch & Ecosystem Pavilion… TSMC Technology Workshop 2024 – Boston
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AI-Driven 3D System Analysis & Optimization for EM Antenna/RF Problems
Antenna/RF design problems often involve the optimization of many variables, requiring numerous evaluations (EM simulations) using traditional optimization methods. Design engineers need an intelligent, accurate, and easy-to-use simulation platform and analysis solution that reduces repetitive design cycles while increasing user productivity and efficiency. Leveraging an advanced AI-enabled methodology, the Cadence Optimality Intelligent System Explorer delivers… AI-Driven 3D System Analysis & Optimization for EM Antenna/RF Problems
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Cracking the Power Code: Innovative Approach to SoC Power Optimization
Power is the biggest factor impacting semiconductors from custom silicon to CPU/GPU products. System-level Power modeling and simulation is needed to measure power accurately and efficiently. The scope of power studies has expanded to include the software, thermal and generation to feed into the UVM/UPF methodology. At this Webinar we will highlight a new system-level… Cracking the Power Code: Innovative Approach to SoC Power Optimization
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Innovative Approach to SoC Power Optimization
Power is the biggest factor impacting semiconductors from custom silicon to CPU/GPU products. System-level Power modeling and simulation is needed to measure power accurately and efficiently. The scope of power studies has expanded to include the software, thermal and generation to feed into the UVM/UPF methodology. At this Webinar we will highlight a new system-level… Innovative Approach to SoC Power Optimization
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ESD Alliance CEO/Executive Outlook
Keysight 5301 Stevens Creek Blvd, Building 5, Santa Clara, United StatesKey executives from leading semiconductor EDA and IP companies will gather to discuss the latest industry trends, challenges and opportunities Thursday, May 9, in Santa Clara, California at the annual CEO Executive Outlook, hosted by the Electronic System Design Alliance (ESD Alliance), a SEMI Technology Community, and Keysight Technologies. Registration is open. Kicking off the program, Calista Redmond, CEO of… ESD Alliance CEO/Executive Outlook
12 events found.