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DVClub India – Ensuring my Design Verification is ISO26262 Compliant
Cadence, Bengaluru Sarjapur Outer Ring Road, Bengaluru, IndiaTBD
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CS Inernational Conference
Sheraton Brussels Airport Hotel Brussels, Belgiumhe 14th CS International builds on the strengths of its predecessors, with around 40 leaders from industry and academia delivering presentations that fall within five key themes: Ensuring SiC’s Phenomenal… CS Inernational Conference
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Streamline MMIC Design Efficiency with Intelligent Design Data Management
In the fast-evolving world of monolithic microwave integrated circuit (MMIC) design, meeting higher-frequency requirements is just the beginning. Are you seeking insights on achieving dimensional accuracy for both analog and… Streamline MMIC Design Efficiency with Intelligent Design Data Management
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Exploring the Advancement of Chiplet Technology and the Ecosystem
Semiconductor companies are making transistors smaller and cramming more into chips to meet the demands of today’s high-tech industries and applications. In fact, in a recent article from the Financial Times, technology… Exploring the Advancement of Chiplet Technology and the Ecosystem
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CadenceLIVE Silicon Valley 2024
Santa Clara Convention Center 5001 Great America Parkway, Santa Clara, CA, United StatesJoin us for CadenceLIVE Silicon Valley 2024 on April 17 at the Santa Clara Convention Center. This annual user conference features peer presentations that offer solutions for today’s design challenges… CadenceLIVE Silicon Valley 2024
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Introduction to ParagonX
Are you ready to supercharge your design process? Introducing our Diakopto Training Program - your gateway to a faster, easier, and more intuitive approach to design analysis and optimization! In… Introduction to ParagonX
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Optimizing Chiplet architectures of RISC-V clusters, GPU and DNN using System-Level IP
Multi-die SoC containing multiple RISC-V clusters, GPU, NPU, accelerators and DNN have considerable benefits for applications in automotive, space and industrial. Architecture exploration of the chiplet-based SoC requires multiple interconnect… Optimizing Chiplet architectures of RISC-V clusters, GPU and DNN using System-Level IP
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Optimizing Chiplet architectures of RISC-V clusters, GPU and DNN using System-Level IP
Multi-die SoC containing multiple RISC-V clusters, GPU, NPU, accelerators and DNN have considerable benefits for applications in automotive, space and industrial. Architecture exploration of the chiplet-based SoC requires multiple interconnect… Optimizing Chiplet architectures of RISC-V clusters, GPU and DNN using System-Level IP
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Latch-Up 2024: Boston
Massachusetts Institute of Technology 77 Massachusetts Avenue, Boston, MA, United StatesFriday to Sunday April 19–21, 2024 in Boston, MA, USA The Latch-Up conference is a weekend of presentations and networking dedicated to free and open source silicon. It's an event… Latch-Up 2024: Boston
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CICC 2024
DoubleTree by Hilton Denver 3203 Quebec Street, Denver, CO, United StatesThe IEEE Custom Integrated Circuits Conference is a premier conference devoted to IC development. The conference program is a blend of oral presentations, exhibits, panels and forums. The conference sessions… CICC 2024
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42nd VLSI Test Symposium
Memorial Union Conference Center 1151 S Forest Ave, Tempe, AZ, United StatesThe IEEE VLSI Test Symposium (VTS) explores emerging trends and novel concepts in test, validation, yield, reliability, and security of microelectronic circuits and systems. The symposium will take place on… 42nd VLSI Test Symposium
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Siemens User2User Verification Forum 2024 India
Hyatt Place, Banjara Hills Road no 1, Banjara Hills, Hyderabad, IndiaJoin us at the Siemens User2User Verification Forum 2024 in India next week! Gain insights on Smart Verification - Using AI in Functional Verification and learn best practices in design… Siemens User2User Verification Forum 2024 India
12 events found.