Aldec
UVM for FPGAs (Part 2): Solving FPGA Verification Challenges with UVM
Abstract: Today’s FPGAs have become larger in logic density and can handle complex designs with multi-million system logic cells. The traditional verification techniques of simple simulations combined with a detailed validation in the lab simply do not scale up any longer. Even to map a large logic design to a modern-day FPGA takes many hours.… Read More »UVM for FPGAs (Part 2): Solving FPGA Verification Challenges with UVM
UVM for FPGAs (Part 3): Verifying Zynq MPSoC Designs?
Learn how UVM Register Access Layer (RAL) can help Presenter: Srinivasan Venkataramanan, Entrepreneur and Head of VerifWorks Thursday, September 23, 2021 Abstract: The use of highly configurable IP-based designs have become the norm in the SoC era. Modern SoC designs targeting Xilinx® Zynq Ultrascale+ MPSoC include an extensive list of standard embedded IPs and custom… Read More »UVM for FPGAs (Part 3): Verifying Zynq MPSoC Designs?
UVM for FPGAs (Part 4): IEEE 1800.2 UVM Updates
Abstract: Started with an early adaptor release as Accellera 1.0a, UVM has evolved into few significant versions including UVM 1.1 and UVM 1.2. As with many popular useful standards, UVM has attained the coveted IEEE standardization in 2017. Interestingly, UVM is the first verification methodology to be standardized, and the current version is IEEE 1800.2-2020.… Read More »UVM for FPGAs (Part 4): IEEE 1800.2 UVM Updates
The most error prone FPGA corner cases
Presenter: Espen Tallaksen, CEO of EmLogic Thursday, October 14, 2021 Abstract: Cycle related corner cases are probably the worst and main reason for undetected bugs on many FPGAs. To explain this in a simple way, - a cycle related corner case is for instance if you have an event counter where the number of counted… Read More »The most error prone FPGA corner cases
Using OVL for Assertion-based Verification of Verilog and VHDL Designs
Open Verification Library (OVL) is a library of property checkers for digital circuit descriptions written in popular Hardware Description Languages and maintained by Accelera. The OVL checkers could be used not only in dynamic simulation, but also in formal verification and emulation. Also, the OVL-based verification technology provides the easiest way for designers to implement… Read More »Using OVL for Assertion-based Verification of Verilog and VHDL Designs
Constraint Random Verification with Python and Cocotb
Abstract: Testing digital hardware has never been an easy job, and it won’t get easier any time soon. But that doesn’t mean writing test code can’t be enjoyable and productive! Cocotb, an approach to use Python as verification language, is bringing the joy back to verification. It allows developers to start with small, directed testbenches,… Read More »Constraint Random Verification with Python and Cocotb
FPGA Conference and Hackathon
We are changing the world through this. So you can! Join the FPGA Hackathon we organize in Kraków to learn more about the technology gaining more and more popularity! Sharing this passion is the reason why we decided to create this Conference and Hackathon. FPGA technology is one of the foundations for the revolutionary projects… Read More »FPGA Conference and Hackathon
LIVE WEBINAR: How to Simplify the Verification of Bus Interfaces (US)
Abstract: Today’s FPGAs and SoC FPGAs use various types of bus interconnect - such as AXI, APB, AHB, Avalon or Wishbone - for both internal (IP-level) and external communication. A recently added feature to Aldec’s ALINT-PRO allows designers to extract, review and verify the correctness of bus interface connections. In addition, ALINT-PRO is capable of… Read More »LIVE WEBINAR: How to Simplify the Verification of Bus Interfaces (US)
Increase your productivity with Continuous Integration flows
Abstract: In a team environment, verification engineers push code changes every day, and sometimes several times a day, to a shared repository. Each change has the potential to introduce new bugs into the design. Accordingly, when many changes are being made, it is difficult to pinpoint which one introduced new bugs, and much time can… Read More »Increase your productivity with Continuous Integration flows
Verification of PCIe-based FPGA Designs Requiring DO-254 Compliance (US)
PCIe-based FPGA designs are becoming popular within avionics systems. However, the verification of such designs for DO-254 compliance with design assurance level (DAL) A or B is problematic. FPGA designs that use asynchronous clocks with multiple high-speed serial interfaces such as PCIe produce non-deterministic results during physical tests. Simulation results are optimized because they are… Read More »Verification of PCIe-based FPGA Designs Requiring DO-254 Compliance (US)