Cadence Integrity
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CadenceTECHTALK: Efficient Multi-Chiplet Design with Integrity 3D-IC Unified Platform
Multi-chiplet design and packaging introduces extra design and analysis requirements like system planning, bump alignment, TSV and micro-bump insertion and extraction, electrothermal analysis, cross-die STA, and inter-die physical verification, which must be considered early during planning and implementation. The new Cadence® Integrity™ 3D-IC platform provides innovative technology that proactively looks ahead through integrated planning, implementation,… CadenceTECHTALK: Efficient Multi-Chiplet Design with Integrity 3D-IC Unified Platform
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CadenceTECHTALK: System Planning and Implementation for Different 3D-IC Design Styles
System planning is a major part of multi-chiplet design. Whether it’s a 2.5-D configuration with an interposer or full-stacked 3D design mounted on a package, it is important to have an automated way to do bump assignment and optimization along with 3D structures implementation. With methodology evolving for different types of designs, a top-down and… CadenceTECHTALK: System Planning and Implementation for Different 3D-IC Design Styles
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CadenceTECHTALK: 3D-IC Chip-Centric Power and Thermal Integrity with High-Performance Hierarchical Analysis
A 3D-IC includes the package, interposer, multiple chiplets, through-silicon vias (TSVs), and through-dielectric vias (TDVs). Supplying power to the chiplets and dissipating heat through these various components poses a major power integrity (PI) and thermal integrity challenge. Early analysis is extremely critical in 3D-ICs, since changing the die stack up later in the design process… CadenceTECHTALK: 3D-IC Chip-Centric Power and Thermal Integrity with High-Performance Hierarchical Analysis
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CadenceTECHTALK: Overcoming System-Level 3D-IC Electrical and Thermal Challenges
Electronic products with 3D-ICs face growing system challenges related to signal, power, and thermal integrity. Design density can lead to performance issues caused by heat, crosstalk, and power noise. In this session, we will address these concerns through simulation during system planning and continuing through signoff to accelerate the 3D-IC design cycle and avoid expensive… CadenceTECHTALK: Overcoming System-Level 3D-IC Electrical and Thermal Challenges