Skip to content
Loading Events

« All Events

  • This event has passed.

CadenceTECHTALK: Efficient Multi-Chiplet Design with Integrity 3D-IC Unified Platform

February 23 @ 10:00 am - 11:00 am PST

Cadence, Multi-Chiplet

Multi-chiplet design and packaging introduces extra design and analysis requirements like system planning, bump alignment, TSV and micro-bump insertion and extraction, electrothermal analysis, cross-die STA, and inter-die physical verification, which must be considered early during planning and implementation. The new Cadence® Integrity™ 3D-IC platform provides innovative technology that proactively looks ahead through integrated planning, implementation, and analysis to address the new requirements of 3D-IC design and signoff for different packaging styles.

In this session, learn about the different packaging styles, innovative multi-technology database, integrated system planner, and an embedded analysis flow manager inside the Integrity 3D-IC platform, which provide a comprehensive, yet modular multi-chiplet design solution to help shorten the design cycle for all aspects of 3D-IC design and signoff.

Details

Date:
February 23
Time:
10:00 am - 11:00 am PST
Event Categories:
,
Event Tags:
, , , ,
Event Website

Organizer

Cadence
View Organizer Website

Leave a Reply

Your email address will not be published.

%d bloggers like this: