CadenceTECHTALK: 3D-IC Chip-Centric Power and Thermal Integrity with High-Performance Hierarchical Analysis

A 3D-IC includes the package, interposer, multiple chiplets, through-silicon vias (TSVs), and through-dielectric vias (TDVs). Supplying power to the chiplets and dissipating heat through these various components poses a major power integrity (PI) and thermal integrity challenge. Early analysis is extremely critical in 3D-ICs, since changing the die stack up later in the design process is incredibly challenging, or not possible.

In this session, get a chip-centric perspective on performing PI and thermal integrity analysis in 3D-ICs from early planning to signoff.