DVClub Europe
RISC-V Verification Strategies
With the popularity of the RISC-V open architecture, many companies are looking for Verification Strategies for developing their own cores or how to verify their integration into a subsystem or SoC. Time Session Description Slides Videos 12.00 GMT Welcome and Introduction Mike Bartley, Senior Vice President – VLSI Design, Tessolve 12.05 GMT RISC-V processor verification… RISC-V Verification Strategies
DVClub Europe: Make Verification Fun Again with Python and cocotb
cocotb is an open source coroutine-based cosimulation testbench environment for verifying VHDL and SystemVerilog RTL using Python. cocotb connects a testbench written in Python with almost all industry-standard simulators. Additionally, cocotb provides a small but powerful framework to efficiently write testcases and run them against a design. cocotb even includes a test runner framework which… DVClub Europe: Make Verification Fun Again with Python and cocotb
DVClub Europe – Best Conference Papers from 2022
Best Conference Papers from 2022 These papers are selected from DVCon and CadenceLive! in 2022 as being most relevant to the DVClub Europe community. Agenda (GMT) 12:00 Welcome and Introduction – Mike Bartley, Tessolve 12:00 Lukas Junger, MachineWare GmbH- SIM-V – Fast, Parallel RISC-V Simulation for Rapid Software Verification 12:30 Josue Quiroga, Barcelona Supercomputing Centre (BSC), Spain;… DVClub Europe – Best Conference Papers from 2022
DVClub Europe – Cache Coherency Verification
This is to inform you that the next DVClub Europe meeting takes place on Tuesday 05th September with a theme of "Cache Coherency Verification". SoC cache coherency verification is one of the most complex challenges faced by verification engineers. And the introduction of the embedded L3 cache and the increasing number of cores in CPU clusters ais making… DVClub Europe – Cache Coherency Verification
Auto-generation of Verification Infrastructure for IP to SoC
Agenda (BST): Time Session Description Slides Videos 12.00 GMT Welcome and Introduction Mike Bartley,Tessolve 12.00 GMT Agnisys 12.30 GMT Imperas 12.45 GMT Breker 13.00 GMT Close About DVClub The principal goal of each DVCLUB meeting is to have fun while helping build the European verification community through regular educational and networking events. Attendance at DVClub Europe… Auto-generation of Verification Infrastructure for IP to SoC
DVClub Europe: Latest VHDL Verification Techniques
This DVClub focuses on the latest verification techniques in VHDL including UVVM and OSVVM Agenda (GMT) 13:00 Welcome and Introduction – Mike Bartley, Tessolve 13:00 Epsen Tallaksen, EmLogic - Get the right FPGA quality through efficient Specification Coverage (aka Requirement Coverage) 13:30 Jim Lewis, SynthWorks - OSVVM in a NutShell, VHDL’s #1 Verification Methodology 14:00 Close Additional… DVClub Europe: Latest VHDL Verification Techniques
DVClub Europe – Formal Verification
13 days to go the next DVClub Europe meeting takes place on Tuesday 23rd April with a theme of "Formal Verification". Formal Verification can help you find bugs earlier in the design cycle and accelerate root cause analysis. But success with Formal requires the effective selection and implementation of the right formal technologies and methods. In this DVClub meeting… DVClub Europe – Formal Verification
DVClub Europe – September 2024
This DVClub event will have talks on verification of low power features of VLSI designs, discussing strategies for accurately measuring power consumption and ensuring that power-saving mechanisms are effective. Additionally, speakers will share insights on how to simulate and analyze different power scenarios to identify potential issues and optimize power management techniques. Attendees will have… DVClub Europe – September 2024
DVClub Europe – AI/ML in Verification
This DVClub will consider how we can save time and effort whilst improving time-to-market through the application of AI/ML to design verification. Agenda (GMT): Time Session Description Slides Videos 12.00 GMT Welcome and Introduction – Mike Bartley, Tessolve Mike Bartley,Tessolve 12.00 GMT Hardik Raina, Agnisys, Inc - Genetic Algorithms for Automated Verification from VCD Data. 12.20… DVClub Europe – AI/ML in Verification
DVClub Europe – Mixed Signal Verification
Edinburgh City Centre Edinburgh, United KingdomAnalog mixed signal chips continue to grow in both demand and complexity, and a consistent efficient verification approach remains a key topic for concern. This DVClub will be held at the Futures Institute at the University of Edinburgh and the university students will be attending. The first half of the DVClub will focus concepts of… DVClub Europe – Mixed Signal Verification