RISC-V
Extending RISC Processors into Flexible Accelerators using ASIP Designer
Case Studies in Low-Power Smart Vision and Post-Quantum Cryptography Applications The slow-down of Moore’s law and Dennard scaling triggered an increased awareness for application-specific instruction-set processors (ASIPs). These processors implement a specialized instruction-set architecture (ISA) tailored to the application domain, often starting from a baseline such as the RISC-V ISA. ASIPs can replace traditional fixed-function… Read More »Extending RISC Processors into Flexible Accelerators using ASIP Designer
Don’t Take the Risk, Formally Verify Your RISC-V Cores
Synopsys Webinar | Thursday, May 25, 2023 | 9:00 a.m. PT According to a recent Semico Research report, the RISC-V Core IP market is expected to grow at a 34.9% CAGR through year 2027. With increasing popularity, it is of utmost importance that the RISC-V Core IPs are secure and bug free. In this… Read More »Don’t Take the Risk, Formally Verify Your RISC-V Cores
SiFive Maximizes Compute Density With Its RISC-V Processor Cores
IP vendor SiFive has been at the forefront of RISC-V’s rapidly growing adoption across a wide array of markets and applications. In this joint presentation with Ansys, SiFive will describe how achieving maximum compute density - compute horsepower per mm2 and per mW (e.g SPECint2006/mm2) - has been a driving goal for SiFive’s portfolio of… Read More »SiFive Maximizes Compute Density With Its RISC-V Processor Cores
RISC-V Summit Europe
Barcelona Barcelona, SpainOn 5-9th June, in Barcelona, RISC-V Summit Europe brings together developers, architects, technical decision and policy makers from across European RISC-V ecosystem. Attendees from academia, research, SMEs, industry and open source communities will gather to exchange knowledge, ideas, technologies, and research shaping the future of RISC-V computing. The event will include a single track of… Read More »RISC-V Summit Europe
GSA 2023 European Executive Forum
Sofitel Munich Bayerpost Bayerstrasse 12, Munich, GermanyDealing with Uncertainty The global economy is sending mixed messages, and with every new data release comes a new batch of upbeat or defeatist headlines. Uncertainty remains if inflation is fully under control and how quickly economic growth will pick up strongly again. On one side the labor market seems healthier than it’s been in… Read More »GSA 2023 European Executive Forum
RISC-V Days Tokyo 2023 Summer
Ito International Research Center The University of Tokyo, Tokyo, JapanRISC-V Day Tokyo 2023 Summer Conference is Japan’s largest RISC-V real event. RISC-V Day Tokyo 2023 Summer Conference will be held on June 20, 2023 (Tuesday) from 9:00 to 20:30 Japan time (JST). A real presentation will be held at Ito Hall ( B2 floor of Ito International Research Center, the University of Tokyo ).… Read More »RISC-V Days Tokyo 2023 Summer
Verification Futures 2023 UK
University of Reading Whiteknights Campus Park House, Reading, United KingdomThe Verification Futures conference provides a unique blend of conference presentations, exhibitions, training and industry networking sessions dedicated to discussing the challenges faced in hardware and software verification. Verification Futures provides a unique opportunity for end-users to define their current and future verification challenges and collaborate with the vendors to create solutions. It also provides… Read More »Verification Futures 2023 UK
2023 Andes RISC-V CON
The DoubleTree by Hilton 2050 Gateway Place, San Jose, CA, United StatesRISC-V is revolutionizing the future of Artificial Intelligence (AI) in industries such as automotive, data center, communications, and IoT. Its open-source instruction set architecture (ISA) provides higher performance, lower power, and compact silicon footprint, features highly desired by these industry segments. RISC-V has gained rapid widespread adoption due to its compact instruction set and extensibility.… Read More »2023 Andes RISC-V CON
Automated Verification for Cache Coherent RISC-V SoCs
RISC-V SoC design complexity continues to increase and create new verification challenges. Private caches, shared caches, and shared main memory create potential caches/memory coherency problems that require modern, automated verification approaches. In this webinar, we’ll demonstrate how Perspec System Verifier, with the pre-defined System Traffic Library (STL), provides an out-of-the-box verification plan and test suite… Read More »Automated Verification for Cache Coherent RISC-V SoCs
A Novel Approach to Implementing Logical ECOs with Synopsys Formality ECO on High Performance RISC-V Cores
RTL engineering change order (ECO) is vital to ensuring proper functionality of integrated circuits (ICs). Retiming and auto ungrouping optimize RTL implementation and enhance PPA. However, aggressive optimizations in CPU RTL designs present challenges due to increased design complexity and potential mapping issues. Synopsys Formality ECO offers an efficient and accurate solution for RTL ECO… Read More »A Novel Approach to Implementing Logical ECOs with Synopsys Formality ECO on High Performance RISC-V Cores
Efficient Bluespec RISC-V Processor Verification for Highest Coverage Closure: A Comprehensive Case Study
The ability to mix and match multiple ISA extensions and add user-defined ISA extensions makes RISC-V verification more challenging than conventional processor verification. This Synopsys webinar demonstrates the verification of standard RISC-V ISA extensions. A subsequent webcast will demonstrate custom ISA verification. The multiple ISA verification problem is solved by RISCV-DV with configurability for ISA… Read More »Efficient Bluespec RISC-V Processor Verification for Highest Coverage Closure: A Comprehensive Case Study
RISC-V in Space
Omni Interlocken Hotel 5000 Interlocken boulevard, Broomfield, CO, United StatesJoin us for "RISC-V in... Space" on November 2, 2023, as we explore the exciting intersection of RISC-V, electronics design, and space! Agenda 9:30 AM - 10:00 AM Registration & Welcome 10:00 AM - 12:00 PM Case Study Presentations: Tenstorrent, Synopsys, RISC AI, Arteris IP 12:00 PM - 1:00 PM Lunch Buffet 1:00 PM - 3:00 PM Case Study Presentations: Breker Systems, Imperas,… Read More »RISC-V in Space