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Webinar Series | RISC-V Ready for Prime Time?
November 16 @ 10:00 am - 11:00 am PST
Join us for session II of our webinar series where we delve into the intricacies of RISC-V core integration and explore strategies to overcome the unique verification challenges that design and verification engineers encounter along the way.
Whether you’re an engineer looking to enhance your understanding of RISC-V or a technology enthusiast keen on staying at the forefront of innovation, this webinar will provide invaluable insights, practical strategies, and real-world examples to help you conquer the verification hurdles associated with RISC-V integration.
Sign Up Here to Get the Zoom Link – https://www.impare.cloud/webinar/session-2
- Introduction to RISC-V: Understanding the modularity and appeal of RISC-V.
- Core Integration Challenges: Exploring the intricacies of integrating RISC-V cores into SoCs, ASICs, and FPGAs.
- Verification Strategies: Unveiling the tools and methodologies to address power, performance, concurrency, inter-core communication, synchronization, security, and safety concerns.
- Real-World Examples: Learning from practical case studies to navigate RISC-V core integration successfully.
- Q&A Session: An opportunity to get your questions answered by our experts.