SoC
UVM for FPGAs (Part 3): Verifying Zynq MPSoC Designs?
Learn how UVM Register Access Layer (RAL) can help Presenter: Srinivasan Venkataramanan, Entrepreneur and Head of VerifWorks Thursday, September 23, 2021 Abstract: The use of highly configurable IP-based designs have become the norm in the SoC era. Modern SoC designs targeting Xilinx® Zynq Ultrascale+ MPSoC include an extensive list of standard embedded IPs and custom… Read More »UVM for FPGAs (Part 3): Verifying Zynq MPSoC Designs?
Agile Planning for SoC Design
Missed milestones, lack of traceability, and costly respins. These are examples of what you risk if you do not take planning seriously during semiconductor design. A rock-solid planning process in the SOC Design process is a must. At the same time, the era of innovation is changing the way teams organize their work. Driven by… Read More »Agile Planning for SoC Design
Avoiding SoC Security Threats – What Verification Engineers Should Know
Thursday, September 30, 2021 | 11:00 -11:30 a.m. PDT The development of secure systems is of paramount importance in this age of software intensive electronic systems. Security weaknesses in the SoC hardware can lead to vulnerabilities that may be exploited later on by malicious software. These challenging problems must be addressed pre-silicon and require rigorous… Read More »Avoiding SoC Security Threats – What Verification Engineers Should Know
LIVE WEBINAR: How to Simplify the Verification of Bus Interfaces (US)
Abstract: Today’s FPGAs and SoC FPGAs use various types of bus interconnect - such as AXI, APB, AHB, Avalon or Wishbone - for both internal (IP-level) and external communication. A recently added feature to Aldec’s ALINT-PRO allows designers to extract, review and verify the correctness of bus interface connections. In addition, ALINT-PRO is capable of… Read More »LIVE WEBINAR: How to Simplify the Verification of Bus Interfaces (US)
Accelerating Complex SoCs Prototyping with Protium X2
This CadenceTECHTALK will offer an overview of the Protium™ Enterprise Prototyping Platform for fast hardware and software verification. We will review the traditional prototyping challenges of complex SoCs using a 5G AI-enabled mobile SoC case study—RTL changes required for clocks management, memories, interfaces, multi-FPGA partitioning, and multi-user support. Join our CadenceTECHTALK to learn how the… Read More »Accelerating Complex SoCs Prototyping with Protium X2
Balancing Performance and Power in adding AI Accelerators to System-on-Chip (SoC)
• Do you need to estimate the power advantage of implementing an AI algorithm on an accelerator? • Do you need to size the AI accelerator for existing and future AI requirements? • Would it be beneficial if you knew the latency advantage between ARM, RISC, DSP and Accelerator in deploying AI tasks? This webinar… Read More »Balancing Performance and Power in adding AI Accelerators to System-on-Chip (SoC)
Power Intent Management for Large SoCs
Defacto Techologie 2 rue Emile Augier, Grenoble, FranceThe complexity of system on chips keeps increasing and SoC designers keep having lot of pressure to deliver and keeping the cost as low as possible. To stay within a PPA budget (power performance area), it's challenging daily for designers. Defacto’s SoC Compiler keep providing innovative solutions to increase the productivity of designers. During this… Read More »Power Intent Management for Large SoCs
Latch-Up 2023
University of California, Santa Barbara Santa Barbara, CA, United StatesThe FOSSi Foundation is proud to announce Latch-Up, a conference dedicated to free and open source silicon to be held over the weekend of Friday, March 31 to Sunday, April 2, 2023 in Santa Barbara, California, USA. Latch-Up is a weekend of presentations and networking for the open source digital design community, much like its European sister conference ORConf. So… Read More »Latch-Up 2023
Boost SoC debug and analytics with embedded software and smart monitors
On-chip monitors and debug structures can dramatically simplify debug, validation, analytics, and optimization of complex SoCs. Such monitors are often accessed by software executing on an external host or debugger via USB or JTAG. In this webinar, we will demonstrate how embedded software running on the target silicon for many use cases provides a superior alternative… Read More »Boost SoC debug and analytics with embedded software and smart monitors