verification
Improving Initial RTL Quality
Development projects, whether FPGA or ASIC SoCs or IP, run into late surprises that quickly result in schedule slips, expensive rework, and/or difficult feature cuts. It is possible to find entire classes of issues without waiting for a testbench. This webinar will introduce you to a testbench-free designer-driven verification flow, resulting in a lower cost… Read More »Improving Initial RTL Quality
Python in Verification Online Meetup
Veriest is inviting you to another event in our series of online Verification Meetups. This time, we'll have two presentations on the polemic topic of using Python in Verification, one by an industry expert and the other by one of Veriest technical leaders. Save the date and watch this space for more details!
Using OVL for Assertion-based Verification of Verilog and VHDL Designs
Open Verification Library (OVL) is a library of property checkers for digital circuit descriptions written in popular Hardware Description Languages and maintained by Accelera. The OVL checkers could be used not only in dynamic simulation, but also in formal verification and emulation. Also, the OVL-based verification technology provides the easiest way for designers to implement… Read More »Using OVL for Assertion-based Verification of Verilog and VHDL Designs
Boost LPDDR5 Verification from IP to System Level
Overview Low power DRAM is being adopted in a wide array of markets, including automotive, PCs and networking systems built for 5G and AI applications. The specification complexity is increasing to meet higher bandwidth, better performance and extended latencies for multiple use cases. Ensuring that JEDEC low-power double data rate 5 (LPDDR5) specification and overall… Read More »Boost LPDDR5 Verification from IP to System Level
Exploring a Software First Approach to Avoid SoC Re-spins
Traditional coverage-based verification methods are no longer sufficient to verify complex SoCs integrating many processor cores and IP subsystems. To conquer the verification challenge of complex SoCs, companies are shifting their development paradigm to a software first approach. By considering the target software up front, as a critical part of the SoC development process, designs… Read More »Exploring a Software First Approach to Avoid SoC Re-spins
Veriest – Verification Meetup in Budapest
Regus Milpark Center 44 Soroksári St., Budapest, HungaryAt Veriest, we believe in knowledge sharing. In our recent meetup events, hundreds of professionals from 20+ different countries gathered to listen to different industry experts from companies such as Intel, ST Microelectronics, arm, Texas Instruments, Nvidia and more. This time, we’ll host our first event in Budapest. Mr. Szabolcs Szolnoki, from the Hungarian Innovation agency, will… Read More »Veriest – Verification Meetup in Budapest
Scalable, On-Demand (by the Minute) Verification to Reach Coverage Closure
Verification has long been the most time-consuming and often resource-intensive part of chip development. Building out the infrastructure to tackle verification can be a costly endeavor, however. Emerging and even well-established semiconductor companies must weigh the Cost-of-Results (COR) against Time-to-Results (TTR) and Quality-of-Results (QOR). The Synopsys Cloud Verification Instance is the first scalable, on-demand verification… Read More »Scalable, On-Demand (by the Minute) Verification to Reach Coverage Closure
Synopsys Verification Technical Symposium 2023 – Israel
Daniel Herzliya Hotel Ramat Yam St 60, Herzliya, IsraelJoin us for a day filled with insights, innovation, and networking in the semiconductor industry. The verification landscape is evolving, and we're here to help you navigate it. At this symposium, we’ll be going through some of the most challenging use cases in chip design today, while exploring best practices and the latest innovations for… Read More »Synopsys Verification Technical Symposium 2023 – Israel
DVClub India – Using AI/ML in Design Verification
Cadence, Bengaluru Sarjapur Outer Ring Road, Bengaluru, IndiaThis DVClub consider how we can save time and effort whilst improving time-to-market through the application of AI/ML to verification. Venue – Cadence Design System, Bengaluru & Online Time Session 15:00 GMT Welcome and introduction - Mike Bartley, Tessolve 15:00 GMT Cadence 16:00 GMT Tessolve 16:30 GMT TBD 17:00 GMT Close About DVClub The principal… Read More »DVClub India – Using AI/ML in Design Verification