VHDL
Using OVL for Assertion-based Verification of Verilog and VHDL Designs
Open Verification Library (OVL) is a library of property checkers for digital circuit descriptions written in popular Hardware Description Languages and maintained by Accelera. The OVL checkers could be used not only in dynamic simulation, but also in formal verification and emulation. Also, the OVL-based verification technology provides the easiest way for designers to implement… Read More »Using OVL for Assertion-based Verification of Verilog and VHDL Designs
Everything you wanted to know about VHDL configurations
VHDL configurations are a much maligned, much ignored part of the VHDL language. Consequently, many VHDL designers find them quite scary. This webinar seeks to answer the questions you may not have had answered in the past; shedding light on the mystery of VHDL configurations and showing a practical example of how to apply them,… Read More »Everything you wanted to know about VHDL configurations
FPGA Verification Architecture Optimization with UVVM
Presenter: Espen Tallaksen, CEO of EmLogic Thursday, May 5, 2022 Abstract: For most FPGA projects, over 50% of the overall project time is spent on verification. This time can be significantly reduced if the verification architecture is well-structured and developed with a focus on reuse. In this webinar, we will show you how to make… Read More »FPGA Verification Architecture Optimization with UVVM
Better FPGA Verification with VHDL: OSVVM – Leading Edge Verification for the VHDL Community
OSVVM is an advanced verification methodology that defines a VHDL verification framework, verification utility library, verification component library, and a scripting flow that simplifies your FPGA verification projects from start to finish. Using these libraries, you can create a simple, readable, and powerful testbench that is suitable for either simple or complex FPGA blocks. Looking… Read More »Better FPGA Verification with VHDL: OSVVM – Leading Edge Verification for the VHDL Community
Better FPGA Verification with VHDL – Faster than “Lite” Verification Component Development with OSVVM
Some methodologies (or frameworks) are so complex that you need a script to create the initial starting point for writing verification components, test cases, and/or the test harness. SystemVerilog + UVM is certainly like this. There are even several organizations that propose that you use their "Lite" or "Easy" approach. Creating a verification component (VC)… Read More »Better FPGA Verification with VHDL – Faster than “Lite” Verification Component Development with OSVVM
OSVVM’s Test Reports and Simulator Independent Scripting
According to the 2020 Wilson Verification Survey FPGA verification engineers spend 46% of their time debugging. As a result, we need good scripting to simplify running tests and good reports to simplify debug and help find problems quickly. Scripting can be complicated no matter what language – particularly with EDA tools that need to stay… Read More »OSVVM’s Test Reports and Simulator Independent Scripting
Advances in OSVVM’s Verification Data Structures
OSVVM has grown tremendously over the last couple of years. This period saw simulator independent scripting, test reporting, model independent transactions, virtual transaction interfaces, and additional verification components, each added and incrementally improved. We have talked about these previously in this webinar series. This webinar focuses on advances in OSVVM data structures. OSVVM's Functional Coverage,… Read More »Advances in OSVVM’s Verification Data Structures
Centralized Register Design and Verification from a Golden Specification
Learn how to bring the ease of a document editor to your system architects and designers to create an executable specification using IDesignSpec™. This specification fully describes and documents your design and automatically generates all downstream views. IDesignSpec™ enables IP, SoC, and FPGA teams to standardize on your register specification and generate Verilog, VHDL, UVM, C… Read More »Centralized Register Design and Verification from a Golden Specification
Sigasi September Productivity Hacks Workshop
Sigasi Studio serves as a code browser for VHDL, Verilog and SystemVerilog. You can navigate through your project to understand large and complex legacy designs. Visuals of your code update instantly and are cross-linked to your code to allow graphical browsing. Sigasi Studio guides you through complex code designs. The instant feedback on errors and… Read More »Sigasi September Productivity Hacks Workshop