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Centralized Register Design and Verification from a Golden Specification

August 18 @ 10:00 am - 11:00 am PDT

Agnisys, August 18, 2022

Learn how to bring the ease of a document editor to your system architects and designers to create an executable specification using IDesignSpec™. This specification fully describes and documents your design and automatically generates all downstream views.

IDesignSpec™¬†enables IP, SoC, and FPGA teams to standardize on your register specification and generate Verilog, VHDL, UVM, C headers, Word, Excel, PDF, and many other formats from it. IDesignSpec is currently available as a plug-in to Word and, Excel, and as a batch utility.

Details

Date:
August 18
Time:
10:00 am - 11:00 am PDT
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Organizer

Agnisys
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