The Open Component Portability Infrastructure (OpenCPI) is an open source software (OSS) framework for developing and executing component-based applications on heterogeneous systems. By targeting heterogeneous… Read More »Introduction to OpenCPI (US)
OSVVM has grown tremendously over the last couple of years. This period saw simulator independent scripting, test reporting, model independent transactions, virtual transaction interfaces, and… Read More »Advances in OSVVM’s Verification Data Structures
According to the 2020 Wilson Verification Survey FPGA verification engineers spend 46% of their time debugging. As a result, we need good scripting to simplify… Read More »OSVVM’s Test Reports and Simulator Independent Scripting
Some methodologies (or frameworks) are so complex that you need a script to create the initial starting point for writing verification components, test cases, and/or… Read More »Better FPGA Verification with VHDL – Faster than “Lite” Verification Component Development with OSVVM
OSVVM is an advanced verification methodology that defines a VHDL verification framework, verification utility library, verification component library, and a scripting flow that simplifies your… Read More »Better FPGA Verification with VHDL: OSVVM – Leading Edge Verification for the VHDL Community
Functional coverage is often mentioned together with constrained-random verification, and this is a great combination. However, functional coverage is also very useful even if you… Read More »FPGA Design/Verification: Code, Functional and Specification Coverage
Randomization is very important for modern verification. Still, very few designers apply randomization sufficiently in their testbenches. This means they are missing out on a… Read More »FPGA Design/Verification: Randomization
Presenter: Espen Tallaksen, CEO of EmLogic Thursday, May 5, 2022 Abstract: For most FPGA projects, over 50% of the overall project time is spent on… Read More »FPGA Verification Architecture Optimization with UVVM
The FPGA design architecture is the single most important and primary factor in achieving development efficiency, quality and reliability. The difference between a good and… Read More »Webinar: FPGA Design Architecture Optimization
Designing FPGAs that use a single clock domain is a luxury that very few of us have. Modern FPGA designs must cope with multiple clocks… Read More »Running CDC Analysis with Xilinx Parameterized Macros