FPGA Conference Europe
The FPGA Conference Europe, organized by ELEKTRONIKPRAXIS and the FPGA training center PLC2, is Europe’s leading specialist conference for programmable logic devices. The conference focusses… Read More »FPGA Conference Europe
The FPGA Conference Europe, organized by ELEKTRONIKPRAXIS and the FPGA training center PLC2, is Europe’s leading specialist conference for programmable logic devices. The conference focusses… Read More »FPGA Conference Europe
Abstract: This demonstrated tutorial is intended for designers and verification engineers who want to learn to make better and more structured testbenches. This session will… Read More »Making a Structured VHDL Testbench – A Demo for Beginners
Based on recent industry research, the FPGA market was valued at approximately USD 7.5 Billion in 2023, with an expected compound annual growth rate (CAGR)… Read More »High-Performance RTL Simulation Workflow with Libero and Active-HDL
Based on recent industry research, the FPGA market was valued at approximately USD 7.5 Billion in 2023, with an expected compound annual growth rate (CAGR)… Read More »High-Performance RTL Simulation Workflow with Quartus and Active-HDL
Based on recent industry research, the FPGA market was valued at approximately USD 7.5 Billion in 2023, with an expected compound annual growth rate (CAGR)… Read More »High-Performance RTL Simulation Workflow with Vivado and Active-HDL
This “Getting Started” webinar focuses on the first, essential steps you need to take when looking to improve your VHDL testbench approach. In this webinar… Read More »Essential Steps to Simplify VHDL Testbenches Using OSVVM
AXI has become the most popular internal bus protocol with today’s FPGA and SoC FPGA designs. ALINT-PRO enables FPGA designers to extract, review and statically… Read More »Verifying AXI Interconnects with ALINT-PRO and Riviera-PRO
Previous years: 2022 2021 2020 2019 2018 2017 2016 The @AgileAnalog team would like to send Season’s Greetings to all our customers and partners across the globe. It has been another… Read More »Happy Hanukkah, Merry Christmas – 2023
cocotb enables Python-based hardware verification, and it integrates into your simulator of choice, such as Aldec’s Riviera-PRO and executes Python testbenches in that context. In… Read More »Ways to run cocotb: makefiles, cocotb-test, or your custom setup
AVersal ACAP, developed by Xilinx/AMD, is a groundbreaking adaptable platform composed of AI Engine (AIE), Processing System (PS), Programmable Logic (PL), Network on Chip (NoC)… Read More »System Simulation of Versal ACAP Designs