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Aldec, June 23, 2022

Advances in OSVVM’s Verification Data Structures

OSVVM has grown tremendously over the last couple of years. This period saw simulator independent scripting, test reporting, model independent transactions, virtual transaction interfaces, and… Read More »Advances in OSVVM’s Verification Data Structures

Aldec, June 16, 2022

OSVVM’s Test Reports and Simulator Independent Scripting

According to the 2020 Wilson Verification Survey FPGA verification engineers spend 46% of their time debugging.  As a result, we need good scripting to simplify… Read More »OSVVM’s Test Reports and Simulator Independent Scripting

Aldec, May 26, 2022

Better FPGA Verification with VHDL: OSVVM – Leading Edge Verification for the VHDL Community

OSVVM is an advanced verification methodology that defines a VHDL verification framework, verification utility library, verification component library, and a scripting flow that simplifies your… Read More »Better FPGA Verification with VHDL: OSVVM – Leading Edge Verification for the VHDL Community

Aldec, May 19, 2022

FPGA Design/Verification: Code, Functional and Specification Coverage

Functional coverage is often mentioned together with constrained-random verification, and this is a great combination. However, functional coverage is also very useful even if you… Read More »FPGA Design/Verification: Code, Functional and Specification Coverage

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