A logic simulator’s programming interfaces can be used for not only verifying logic IP but also the co-development of logic and embedded software. Our ‘Introducing… Read More »The Power of Verilog’s PLI and VPI for FPGA Designs
The use of advanced verification tools can significantly reduce the number of non-trivial bugs, save engineering time and resources and, more importantly, increase the reliability… Read More »Linting and Clock Domain Crossing Analysis for Microchip FPGA Designs
The embedded world Exhibition&Conference provides a global platform and a place to meet for the entire embedded community, including leading experts, key players and industry… Read More »Embedded World
Writing code is easy. Reading code is hard. Maintaining code is hard. Writing “good” code is hard. So what’s “good code”? Don’t despair: the software… Read More »Engineering best practices for Python-based testbenches with cocotb
Coverage is an essential part of any verification environment. Coverage can be simple as a statement and branch coverage, or it can be more complex… Read More »Optimizing Simulations for Efficient Coverage Collection
Assertion-based verification (ABV) enables the use of assertions for the efficient verification of low-level design properties. These assertions could be verified by simulation and formal… Read More »Assertions-Based Verification for VHDL Designs
Most FPGA designs contain configurable hard IP blocks supplied by FPGA vendors. These Hard IP blocks do not contain synthesizable RTL code, and therefore are… Read More »CDC Verification with Hard IP Blocks
OSVVM has grown tremendously over the last couple of years. This period saw simulator independent scripting, test reporting, model independent transactions, virtual transaction interfaces, and… Read More »Advances in OSVVM’s Verification Data Structures
According to the 2020 Wilson Verification Survey FPGA verification engineers spend 46% of their time debugging. As a result, we need good scripting to simplify… Read More »OSVVM’s Test Reports and Simulator Independent Scripting
Some methodologies (or frameworks) are so complex that you need a script to create the initial starting point for writing verification components, test cases, and/or… Read More »Better FPGA Verification with VHDL – Faster than “Lite” Verification Component Development with OSVVM