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Aldec

Aldec, April 4, 2024

High-Performance RTL Simulation Workflow with Libero and Active-HDL

Based on recent industry research, the FPGA market was valued at approximately USD 7.5 Billion in 2023, with an expected compound annual growth rate (CAGR)… Read More »High-Performance RTL Simulation Workflow with Libero and Active-HDL

Aldec, March 28, 2024

High-Performance RTL Simulation Workflow with Quartus and Active-HDL

Based on recent industry research, the FPGA market was valued at approximately USD 7.5 Billion in 2023, with an expected compound annual growth rate (CAGR)… Read More »High-Performance RTL Simulation Workflow with Quartus and Active-HDL

Aldec, March 21, 2024

High-Performance RTL Simulation Workflow with Vivado and Active-HDL

Based on recent industry research, the FPGA market was valued at approximately USD 7.5 Billion in 2023, with an expected compound annual growth rate (CAGR)… Read More »High-Performance RTL Simulation Workflow with Vivado and Active-HDL

Cadence

Happy Hanukkah, Merry Christmas – 2023

Previous years: 2022 2021 2020 2019 2018 2017 2016 The @AgileAnalog team would like to send Season’s Greetings to all our customers and partners across the globe. It has been another… Read More »Happy Hanukkah, Merry Christmas – 2023

Aldec, November 9, 2023

Ways to run cocotb: makefiles, cocotb-test, or your custom setup

cocotb enables Python-based hardware verification, and it integrates into your simulator of choice, such as Aldec’s Riviera-PRO and executes Python testbenches in that context. In… Read More »Ways to run cocotb: makefiles, cocotb-test, or your custom setup