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Aldec, March 2, 2023

Linting and Clock Domain Crossing Analysis for Microchip FPGA Designs

The use of advanced verification tools can significantly reduce the number of non-trivial bugs, save engineering time and resources and, more importantly, increase the reliability… Read More »Linting and Clock Domain Crossing Analysis for Microchip FPGA Designs

Aldec, November 10, 2022

Engineering best practices for Python-based testbenches with cocotb

Writing code is easy. Reading code is hard. Maintaining code is hard. Writing “good” code is hard. So what’s “good code”? Don’t despair: the software… Read More »Engineering best practices for Python-based testbenches with cocotb

Aldec, June 23, 2022

Advances in OSVVM’s Verification Data Structures

OSVVM has grown tremendously over the last couple of years. This period saw simulator independent scripting, test reporting, model independent transactions, virtual transaction interfaces, and… Read More »Advances in OSVVM’s Verification Data Structures

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