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fpga hackathon

FPGA Conference and Hackathon

We are changing the world through this. So you can! Join the FPGA Hackathon we organize in Kraków to learn more about the technology gaining more and more popularity! Sharing this passion is the reason… 

Aldec Oct 14

The most error prone FPGA corner cases

Presenter: Espen Tallaksen, CEO of EmLogic Thursday, October 14, 2021 Abstract: Cycle related corner cases are probably the worst and main reason for undetected bugs on many FPGAs. To explain this in a simple way,… 

Aldec UVM part 4

UVM for FPGAs (Part 4): IEEE 1800.2 UVM Updates

Abstract: Started with an early adaptor release as Accellera 1.0a, UVM has evolved into few significant versions including UVM 1.1 and UVM 1.2.  As with many popular useful standards, UVM has attained the coveted IEEE… 

Sep 23 Aldec

UVM for FPGAs (Part 3): Verifying Zynq MPSoC Designs?

Learn how UVM Register Access Layer (RAL) can help Presenter: Srinivasan Venkataramanan, Entrepreneur and Head of VerifWorks Thursday, September 23, 2021 Abstract: The use of highly configurable IP-based designs have become the norm in the… 

EDA and Semi clients or blogs

Blog Updates for 2021

We’re already into the new year, so it was about time that I updated my list of Semi and EDA vendors that I’ve blogged or consulted for, here’s what changed: Mentor became Siemens EDA Moortec… 

QMAX Systems

Merry Christmas 2019

Celebrate Christmas and the New Year, so send me your greetings to be shared here annually. Happy New Years is here. 2018 2017 2016 2015

Telesales works in EDA

EMA has been selling the OrCAD product line to PCB designers for several years now so it makes sense as they broaden their product lines to add the Aldec tools. My only question about this…