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Aldec Oct 14

The most error prone FPGA corner cases

Presenter: Espen Tallaksen, CEO of EmLogic Thursday, October 14, 2021 Abstract: Cycle related corner cases are probably the worst and main reason for undetected bugs on many FPGAs. To explain this in a simple way,… The most error prone FPGA corner cases

Aldec October 21

Using OVL for Assertion-based Verification of Verilog and VHDL Designs

Open Verification Library (OVL) is a library of property checkers for digital circuit descriptions written in popular Hardware Description Languages and maintained by Accelera. The OVL checkers could be used not only in dynamic simulation,… Using OVL for Assertion-based Verification of Verilog and VHDL Designs

Aldec UVM part 4

UVM for FPGAs (Part 4): IEEE 1800.2 UVM Updates

Abstract: Started with an early adaptor release as Accellera 1.0a, UVM has evolved into few significant versions including UVM 1.1 and UVM 1.2.  As with many popular useful standards, UVM has attained the coveted IEEE… UVM for FPGAs (Part 4): IEEE 1800.2 UVM Updates

Sep 23 Aldec

UVM for FPGAs (Part 3): Verifying Zynq MPSoC Designs?

Learn how UVM Register Access Layer (RAL) can help Presenter: Srinivasan Venkataramanan, Entrepreneur and Head of VerifWorks Thursday, September 23, 2021 Abstract: The use of highly configurable IP-based designs have become the norm in the… UVM for FPGAs (Part 3): Verifying Zynq MPSoC Designs?

Aldec Sept 16

UVM for FPGAs (Part 2): Solving FPGA Verification Challenges with UVM

Abstract: Today’s FPGAs have become larger in logic density and can handle complex designs with multi-million system logic cells. The traditional verification techniques of simple simulations combined with a detailed validation in the lab simply… UVM for FPGAs (Part 2): Solving FPGA Verification Challenges with UVM