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Aldec, Verification

FPGA Design Verification – Advanced Testbench Implementation

Abstract As FPGA technology continues to evolve – to provide us with full-blown SoCs with CPU, GPU, and high-speed peripherals, for example, joining the traditional… Read More »FPGA Design Verification – Advanced Testbench Implementation

Aldec, March 2, 2023

Linting and Clock Domain Crossing Analysis for Microchip FPGA Designs

The use of advanced verification tools can significantly reduce the number of non-trivial bugs, save engineering time and resources and, more importantly, increase the reliability… Read More »Linting and Clock Domain Crossing Analysis for Microchip FPGA Designs

Aldec, November 10, 2022

Engineering best practices for Python-based testbenches with cocotb

Writing code is easy. Reading code is hard. Maintaining code is hard. Writing “good” code is hard. So what’s “good code”? Don’t despair: the software… Read More »Engineering best practices for Python-based testbenches with cocotb