Skip to content
Aldec, February 15, 2024

Essential Steps to Simplify VHDL Testbenches Using OSVVM

This “Getting Started” webinar focuses on the first, essential steps you need to take when looking to improve your VHDL testbench approach. In this webinar we examine transaction-based testing, self-checking tests, messaging, reports, and Open… 

Aldec, January 25,2024

Verifying AXI Interconnects with ALINT-PRO and Riviera-PRO

AXI has become the most popular internal bus protocol with today’s FPGA and SoC FPGA designs. ALINT-PRO enables FPGA designers to extract, review and statically verify AXI bus interfaces. In addition, ALINT-PRO can assist with… 

Cadence

Happy Hanukkah, Merry Christmas – 2023

Previous years: 2022 2021 2020 2019 2018 2017 2016 The @AgileAnalog team would like to send Season’s Greetings to all our customers and partners across the globe. It has been another busy year and we look forward to delivering more of… 

Aldec, November 9, 2023

Ways to run cocotb: makefiles, cocotb-test, or your custom setup

cocotb enables Python-based hardware verification, and it integrates into your simulator of choice, such as Aldec’s Riviera-PRO and executes Python testbenches in that context. In this webinar, we will look at ways to invoke your… 

Aldec, November 16, 2023

System Simulation of Versal ACAP Designs

AVersal ACAP, developed by Xilinx/AMD, is a groundbreaking adaptable platform composed of AI Engine (AIE), Processing System (PS), Programmable Logic (PL), Network on Chip (NoC) and a wide range of hardened domain-specific IPs. Versal ACAP… 

Aldec, August 31, 2023

Advanced Testbench for a Complex DUT

Functional simulation using an HDL testbench is the de facto method for proving functional correctness of FPGA designs. In this three-part webinar series, we will present a step-by-step approach on how to architect a testbench… 

Aldec, Verification

FPGA Design Verification – Advanced Methods

Abstract As FPGA technology continues to evolve – to provide us with full-blown SoCs with CPU, GPU, and high-speed peripherals, for example, joining the traditional programmable logic area – design verification becomes increasingly challenging. Lab-based…