High-Level Synthesis (HLS) tools yield better PPA when the “right set” of optimization constraints and tool settings are applied. Determining the right set of constraints and settings requires design and tool experience and exploration. AI/ML… An AI/ML Driven High-Level Synthesis Solution
Day 1 June 27th, 2023 12:00 – 1:00pm PDT Networking Lunch & Registration 1:00 – 1:05pm PDT Opening Jinman Han EVP, Head of DSA Office, Samsung Electronics 1:05 – 1:20pm PDT Samsung Keynote Siyoung Choi President… SFF & SAFE™ Forum 2023 San Jose, CA
The Design & Verification Conference & Exhibition is the premier conference on the application of languages, tools, methodologies and standards for the design and verification of electronic systems and integrated circuits. The focus of this… DVCon Japan 2023
As designs get increasingly complex, design teams are looking to find bugs earlier, to reduce rework and shorten time-to-market. The ultimate “shift left” is to put easy-to-use static verification in the hands of RTL designers… Comprehensive Static Verification for FPGA and ASIC RTL Designers
The Verification Futures conferences is dedicated to discussing the challenges faced in hardware and software verification. To view the agenda for this event please visit the VF2023 Event Page. The full conference program includes 17 talks covering… Verification Futures 2023 Austin
Keynote speakers Fadi Maamari VP of Engineering at Synopsys Sule Ozev Arizona State University About Us International Test Conference is the world’s premier venue dedicated to the electronic test of devices, boards and systems-covering the… ITC India 2023
Verisium Debug offers comprehensive debugging capabilities. From RTL, UVM testbench to UPF low-power designs, users can use the Cadence unified debugging platform for debugging. In this webinar, users will learn about the available features in… Verisium Debug for UPF Low Power Design
Ready to share and discuss the latest design and verification best practices with your peers from around the world? It’s time for our annual CadenceCONNECT: Jasper™ User Group Conference, held on October 18 and 19… Jasper User Group 2023
The PCI-SIG Developers Conference 2023 is returning to Santa Clara on June 13-14, 2023! Members of the PCI-SIG community including systems architects, designers, engineers, and engineering managers agree that this is an event you won’t want… PCI-SIG Developers Conference 2023
The problem of optimization is a long-standing one in the field of design. For years, the most conventional approach was the brute-force method of running parametric sweeps on the design space. However, as systems become… Applying AI/ML Technology for Rapid Design Optimization