For the last seventeen years, CadenceLIVE has brought together technology users, developers, and industry experts to connect, share ideas and best practices, and inspire design creativity. Attendees will have the opportunity to view exciting keynotes,… CadenceLIVE Europe
“GLOBAL SEMICONDUCTOR INNOVATION AND OUTLOOK” CASPA invites you to attend our 2021 Virtual Annual Conference on Saturday, October 16th, 2021 via Zoom. This Conference is a signature annual event for CASPA and has been well… CASPA 2021 Annual Conference
International Test Conference, the cornerstone of TestWeek™ events, is the world’s premier conference dedicated to the electronic test of devices, boards and systems-covering the complete cycle from design verification, test, diagnosis, failure analysis and back… Iternational Test Conferece
Overview The Cadence® Celsius™ Thermal Solver is now integrated with the Cadence AWR Design Environment® V16 platform, supporting electrothermal analysis for MMIC/RFIC, PCB, and module designs. Thermal analysis provides RF circuit designers with insight regarding operating… Thermal Analysis for MMIC and RF PCB Power Applications
For more than a decade, The Linley Group has delivered the industry’s premier processor conferences. This year, the Linley Fall Processor Conference will return to Santa Clara on October 20-21, 2021. If you can’t attend… Linley Fall Processor Conference 2021
The Design and Verification Conference in Europe (DVCon Europe) is the leading European event covering the application of languages, tools and intellectual property for the design and verification of electronic systems and integrated circuits. Sponsored… DVCon Europe 2021
Overview Many design teams have used some form of hardware verification throughout their verification cycle for years now. Some engineering teams prefer to use emulation, some prefer to use prototyping, and some even use both.… Benefits of a Common Methodology for Emulation and Prototyping
Join Cadence® Training and Product Engineering Architect Joerg Mueller and Senior Application Engineer Tom Weiss for this free technical training webinar. As a chip designer, you’re probably spending as much headspace on security threats as… Addressing Growing Security Challenges with JasperGold
Analog and mixed-signal verification has always been a challenge for design and verification engineers. It has become tedious with the increasing complexity of SoC designs. Join this webinar to learn how Cadence is providing effective… Cadence TECHTALK: Mixed-Signal SoC Verification Simplified with Xcelium Simulator (NA)
It’s time for our annual formal verification user group CadenceCONNECT: Jasper User Group 2021. This in-depth technical conference connects designers, verification engineers, and engineering managers from around the world to share the latest design and verification… Jasper User Group 2021