It’s time for our inaugural CadenceCONNECT: Conformal® User Group Conference and Technology Day held on December 5th at the Cadence San Jose campus. This interactive, in-depth technical… Read More »Conformal User Group Conference 2023 and Technology Day
Would you like to know how to design a complete chip using the RTL-to-GDSII Flow? In this free technical Training Webinar with Application Engineer Sai… Read More »RTL-to-GDSII Flow for ASIC Design Using Cadence Tools
Today’s electronic products increasingly use Rigid-Flex PCBs to compress form factors, reduce weight, and increase cost-effectiveness. For many commercially available 3D numerical solver technologies (FEM and… Read More »Rigid Flex PCB In-Design Electromagnetic Analysis Workflow
Wall-modeled large eddy simulations (WMLES) of complex vehicle geometries offer highly accurate results but can be challenging in terms of speed and cost. In this… Read More »Large Eddy CFD Simulation for Automotive Aerodynamics
Agenda (BST): Time Session Description Slides Videos 12.00 GMT Welcome and Introduction Mike Bartley,Tessolve 12.00 GMT Agnisys 12.30 GMT Imperas 12.45 GMT Breker 13.00 GMT… Read More »Auto-generation of Verification Infrastructure for IP to SoC
High-fidelity simulations in the ever-widening realm of complete systems analysis requires incorporating vendor-supplied models for accuracy. However, vendors are reluctant to share their proprietary intellectual… Read More »Enabling Electromagnetic Simulations with Encrypted Components
Event Overview Date: Monday, November 13, 2023 Time: 8:30am – 4:00pm, followed by an exclusive networking event Location: Cadence Headquarters, San Jose, CA There is an unprecedented demand… Read More »CadenceCONNECT: The Race Is On!
STAC Summits bring together CTOs and other industry leaders responsible for solution architecture, infrastructure engineering, application development, machine learning/deep learning engineering, data engineering, and operational… Read More »STAC Summit
Are you ready to lead the way in gate-level digital simulations (GLS)? Dive into Cadence’s exclusive webinar and uncover the revolutionary Xcelium Multi-Core (MC) App—a… Read More »Warp Speed Gate-Level Simulations with the Xcelium Multi-Core App
This webinar focuses on three specific aspects of the UVM register layer that will help you to model in UVM some of the less obvious… Read More »Deep Dive into the UVM Register Layer: User-Defined Doors, Predictors, and Callbacks