Date: Wednesday, October 18, 2023 Time: 8:30am PT | 10:30am CT | 11:30am ET Join us for this 45-minute webinar to learn how the Cadence-managed, EDA-optimized, ready-to-use,… Read More »Soar to New Heights of Productivity using Cadence Managed Cloud Services
Event Overview Date: Wednesday, October 18, 2023 Time: 8:30am – 4:00pm, followed by an exclusive networking event Location: Brazos Hall, Austin, TX There is an unprecedented demand for… Read More »The Race is On!
Register now and join us at GlobalFoundries Technology Summit 2023! GF Technology Summit (GTS) 2023 is our worldwide, annual series of technology-focused events. GTS brings together leaders… Read More »GTS 2023 – Munich
Verisium Debug offers comprehensive debugging capabilities. From RTL and UVM testbench to UPF low-power designs, Cadence’s unified debugging platform helps users debug. In this webinar,… Read More »Verisium Debug for UVM Testbench
The Largest Conference and Exhibition for Printed Circuit Board Design, Fabrication and Assembly in the Silicon Valley For more than 30 years PCB West has trained designers,… Read More »PCB West 2023
EDPS 2023 is approaching fast! The program is firming up – please see the program page for a preliminary list of talks. REGISTRATION IS NOW OPEN.… Read More »EDPS 2023
Learn About: Emerging advanced node design challenges and corresponding design flows and methodologies for N2, N3/N3E/N3P/N3AE, N4/N4P, N5/N5A, N6/N6e/N6RF/N7, N12e, and N22 Latest updates on… Read More »TSMC 2023 North America OIP Ecosystem Forum
Please join me, Cadence Training and Application Engineer Krishna Atreya, for this free technical Training Webinar. What Is the Webinar About? The Cadence Cerebrus Intelligent… Read More »Cadence Training: Cerebrus Intelligent Chip Explorer
The heterogeneous integration of chips and chiplets in IC packages is all the rage as we face “More than Moore” performance challenges. While these innovative… Read More »Proactively Address Thermal Concerns in Advanced IC Packages
Innovative die disaggregation technologies, enable a future where a catalog of chiplets will be available to mix and match based on the end application. The… Read More »UCIe-Based Chiplet Verification – from IP to SoC