CDC Verification with Hard IP Blocks
Most FPGA designs contain configurable hard IP blocks supplied by FPGA vendors. These Hard IP blocks do not contain synthesizable RTL code, and therefore are… Read More »CDC Verification with Hard IP Blocks
CDC
Constraints-Driven CDC and RDC Verification Including UPF Aware Analysis
Today’s million gates integrated circuits (ICs) involve various intellectual properties (IPs) interfacing with each other through multiple asynchronous clock and reset domains. Ensuring all clocks… Read More »Constraints-Driven CDC and RDC Verification Including UPF Aware Analysis
Running CDC Analysis with Xilinx Parameterized Macros
Designing FPGAs that use a single clock domain is a luxury that very few of us have. Modern FPGA designs must cope with multiple clocks… Read More »Running CDC Analysis with Xilinx Parameterized Macros
Pre-empt Late-stage Low Power Issues using Predictive Analysis
Low power is an increasingly critical requirement for all modern SoCs. Moreover, it is becoming more and more difficult with complex architectures being used in modern designs. This has made… Read More »Pre-empt Late-stage Low Power Issues using Predictive Analysis