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IEEE CAS, December 19, 2024

Signal and Power Integrity Challenges in Advanced Packaging Technologies for Disaggregated Integration

Abstract The integrated circuit industry faces new challenges as chip complexity and area have been increasing to prohibitive ranges. Some segments have been adopting then a relatively new paradigm for heterogeneous integration based on chiplets… Signal and Power Integrity Challenges in Advanced Packaging Technologies for Disaggregated Integration

GSA, February 20, 2025

GSA Mena Executive Summit

On February 20, 2025 in Cairo, Egypt, we are hosting the GSA MENA Executive Summit to look beyond the current divisions and rather recognize the Middle East North Africa regional potential as a source of capital and destination… GSA Mena Executive Summit

Cadence, December 12, 2024

Accelerating SoC Automotive Design with Chiplets

Step into the forefront of innovation with our upcoming webinar, which explores how chiplet technology is revolutionizing the automotive industry and setting new benchmarks. Discover how Cadence is empowering customers to achieve unparalleled success with… Accelerating SoC Automotive Design with Chiplets

EE Times, July 24-25, 2024

Chiplets: Building the Future of SoCs

Chiplets, also known as heterogeneous multi-die systems, are increasingly seen as the future of System on Chips (SoCs). They offer a solution to meet the growing demands of high-performance computing in various industries, particularly fueled… Chiplets: Building the Future of SoCs

Ansys, April 25, 2024

The Era of Software-Defined Everything: Chiplets and Bespoke Silicon

From fintech to automotive, defense to healthcare, everyone wants bespoke computing platforms to build “software-defined solutions” that are differentiated in their respective markets. Sign up and save your spot for this special presentation. Overview With… The Era of Software-Defined Everything: Chiplets and Bespoke Silicon

Cadence, October 12, 2023

Proactively Address Thermal Concerns in Advanced IC Packages

The heterogeneous integration of chips and chiplets in IC packages is all the rage as we face “More than Moore” performance challenges. While these innovative design practices successfully address performance goals, some design teams find… Proactively Address Thermal Concerns in Advanced IC Packages

UCIe, Feb 21, 2023

Introduction to UCIe

UCIe™ — Universal Chiplet Interconnect Express™ — is an open industry standard founded by the leaders in semiconductors, packaging, IP suppliers, foundries, and cloud service providers to address customer requests for more customizable package-level integration.… Introduction to UCIe

TSMC 2022 EU

TSMC 2022 EU OIP Ecosystem Forum

Learn About: Emerging advanced node design challenges and corresponding design flows and methodologies for N3/N3E, N4/N4P, N5/N5A, N6/N7, N12e, N22, and 28eF technologies Latest 3DIC chip stacking and advanced packaging processes, and innovative 3DIC design… TSMC 2022 EU OIP Ecosystem Forum

proteantecs, november 16, 2022

The Era of Chiplets and Heterogeneous Integration: Challenges and Emerging Solutions to Support 2.5D and 3D Advanced Packaging

As the semiconductor industry adopts chiplets and heterogeneous integration for its packaging as a key enabler to the continuation of scaling beyond Moore’s law, it has created new challenges. Join us on Wednesday, November 16… The Era of Chiplets and Heterogeneous Integration: Challenges and Emerging Solutions to Support 2.5D and 3D Advanced Packaging