Versal ACAP Workshop Online
The Xilinx Versal ACAP platform is multi-featured, offering unprecedented system level performance and integration. This informative workshop (delivered in 2 half day sessions) is a… Read More »Versal ACAP Workshop Online
The Xilinx Versal ACAP platform is multi-featured, offering unprecedented system level performance and integration. This informative workshop (delivered in 2 half day sessions) is a… Read More »Versal ACAP Workshop Online
This webinar gives a comprehensive guide to all aspects of SystemVerilog arrays: ordinary static arrays, dynamic arrays, queues and associative arrays. It also includes array… Read More »Everything You Need to Know about SystemVerilog Arrays
It’s time for my annual Christmas and Holiday greetings from Semiconductor, #SemiEDA and #SemiIP companies. Send me your favorites. Past years: 2020 2019 2018 2017 2016 Happy holidays… Read More »Merry Christmas 2021
VHDL configurations are a much maligned, much ignored part of the VHDL language. Consequently, many VHDL designers find them quite scary. This webinar seeks to… Read More »Everything you wanted to know about VHDL configurations
Webinar Overview: A common issue with constrained random simulation is being able to reproduce random stimulus for debug purposes and for locking down regressions test… Read More »Understanding Random Stability in SystemVerilog and UVM
Celebrate Christmas and the New Year, so send me your greetings to be shared here annually. Happy New Years is here. 2018 2017 2016 2015