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Doulos, December 2, 2022

Dealing with Inconclusive Formal Proofs

Formal proofs of end-to-end properties can be a very valuable contribution to RTL sign-off and yet are often the most difficult to achieve. In this webinar Doulos Senior Member Technical Staff, Doug Smith will explore… 

Doulos, September 23, 2022

The Keys to SystemC & TLM-2.0: How to be Successful​

SystemC has become well-established as the language of choice for system modeling and virtual platform creation and integration, and is now being applied successfully for high level synthesis. SystemC models also frequently appear as reference… 

Doulos, June 15, 2022

Debugging Features of UVM

A UVM testbench is a large and complex piece of software. At some stage, like any other large and complex piece of software, a verification environment written using UVM is going to require debugging. There… 

Synopsys, June 1, 2022

Become an SVA Expert in One Hour

Doulos Co-Founder & Technical Fellow John Aynsley will teach the core principles necessary to understand and use SystemVerilog Assertions, focussing on the aspects of SVA that are applicable to both formal verification and simulation. Particular emphasis will… 

Doulos, May 24-25, 2022

Versal ACAP Workshop Online

The Xilinx Versal ACAP platform is multi-featured, offering unprecedented system level performance and integration. This informative workshop (delivered in 2 half day sessions) is a comprehensive and practical introduction to the features and capabilities. We’ll… 

Doulos, February 4, 2022

Everything You Need to Know about SystemVerilog Arrays

This webinar gives a comprehensive guide to all aspects of SystemVerilog arrays: ordinary static arrays, dynamic arrays, queues and associative arrays. It also includes array methods and practical examples. Topics: Review of Verilog array types… 

Merry Christmas 2021

It’s time for my annual Christmas and Holiday greetings from Semiconductor, #SemiEDA and #SemiIP companies. Send me your favorites. Past years: 2020 2019 2018 2017 2016 Happy holidays from all of us at Rambus! pic.twitter.com/ZfzZVgA3V9 — Rambus Inc.… 

VHDL, NOvember 19, 2021

Everything you wanted to know about VHDL configurations

VHDL configurations are a much maligned, much ignored part of the VHDL language. Consequently, many VHDL designers find them quite scary. This webinar seeks to answer the questions you may not have had answered in… 

doulos november 3

Understanding Random Stability in SystemVerilog and UVM

Webinar Overview: A common issue with constrained random simulation is being able to reproduce random stimulus for debug purposes and for locking down regressions test suites. This is especially problematic when the source code needs… 

QMAX Systems

Merry Christmas 2019

Celebrate Christmas and the New Year, so send me your greetings to be shared here annually. Happy New Years is here. 2018 2017 2016 2015