Skip to content

Doulos

Doulos, September 20, 2023

Maximize Design Productivity using Vivado ML with SystemVerilog

Although SystemVerilog is perhaps most widely used in the context of hardware verification, it also contains many features directly relevant to FPGA hardware designers. We… Read More »Maximize Design Productivity using Vivado ML with SystemVerilog

Doulos, June 23, 2023

Dealing with Complexity in Formal through Abstraction and Reduction

In the world of formal verification, abstractions along with design reductions, help reduce the state space and make it easier for formal to converge on… Read More »Dealing with Complexity in Formal through Abstraction and Reduction

%d bloggers like this: