Debugging Features of UVM
A UVM testbench is a large and complex piece of software. Like any other large and complex piece of software, a verification environment written using… Read More »Debugging Features of UVM
Doulos
Verification Futures Conference 2024 Austin
The Verification Futures conference provides a unique blend of conference presentations, exhibitions, training and industry networking sessions dedicated to discussing the challenges faced in hardware… Read More »Verification Futures Conference 2024 Austin
Verification Futures Conference 2024 UK
The Verification Futures conference provides a unique blend of conference presentations, exhibitions, training and industry networking sessions dedicated to discussing the challenges faced in hardware… Read More »Verification Futures Conference 2024 UK
DVCon USA 2024
The Design & Verification Conference & Exhibition is the premier conference on the application of languages, tools, methodologies and standards for the design and verification… Read More »DVCon USA 2024
Happy Hanukkah, Merry Christmas – 2023
Previous years: 2022 2021 2020 2019 2018 2017 2016 The @AgileAnalog team would like to send Season’s Greetings to all our customers and partners across the globe. It has been another… Read More »Happy Hanukkah, Merry Christmas – 2023
Debugging SystemC with GDB
Webinar Overview: This webinar explores debugging SystemC code with basic tools, including issues and strategies to make improvements. A large portion of the webinar includes… Read More »Debugging SystemC with GDB
Deep Dive into the UVM Register Layer: User-Defined Doors, Predictors, and Callbacks
This webinar focuses on three specific aspects of the UVM register layer that will help you to model in UVM some of the less obvious… Read More »Deep Dive into the UVM Register Layer: User-Defined Doors, Predictors, and Callbacks
Maximize Design Productivity using Vivado ML with SystemVerilog
Although SystemVerilog is perhaps most widely used in the context of hardware verification, it also contains many features directly relevant to FPGA hardware designers. We… Read More »Maximize Design Productivity using Vivado ML with SystemVerilog
Everything You Need to Know about SystemVerilog Arrays
This webinar gives a comprehensive guide to all aspects of SystemVerilog arrays: ordinary static arrays, dynamic arrays, queues and associative arrays. It also includes array… Read More »Everything You Need to Know about SystemVerilog Arrays
Dealing with Inconclusive Formal Proofs
Webinar Overview: Formal proofs of end-to-end properties can be a very valuable contribution to RTL sign-off and yet are often the most difficult to achieve.… Read More »Dealing with Inconclusive Formal Proofs