Analog mixed signal chips continue to grow in both demand and complexity, and a consistent efficient verification approach remains a key topic for concern. This DVClub will be held at the Futures Institute at the… DVClub Europe – Mixed Signal Verification
This DVClub will consider how we can save time and effort whilst improving time-to-market through the application of AI/ML to design verification. Agenda (GMT): Time Session Description Slides Videos 12.00 GMT Welcome and Introduction –… DVClub Europe – AI/ML in Verification
This DVClub event will have talks on verification of low power features of VLSI designs, discussing strategies for accurately measuring power consumption and ensuring that power-saving mechanisms are effective. Additionally, speakers will share insights on… DVClub Europe – September 2024
13 days to go the next DVClub Europe meeting takes place on Tuesday 23rd April with a theme of “Formal Verification“. Formal Verification can help you find bugs earlier in the design cycle and accelerate root cause analysis. But… DVClub Europe – Formal Verification
This DVClub focuses on the latest verification techniques in VHDL including UVVM and OSVVM Agenda (GMT) 13:00 Welcome and Introduction – Mike Bartley, Tessolve 13:00 Epsen Tallaksen, EmLogic – Get the right FPGA quality through efficient… DVClub Europe: Latest VHDL Verification Techniques
Agenda (BST): Time Session Description Slides Videos 12.00 GMT Welcome and Introduction Mike Bartley,Tessolve 12.00 GMT Agnisys 12.30 GMT Imperas 12.45 GMT Breker 13.00 GMT Close About DVClub The principal goal of each DVCLUB meeting is… Auto-generation of Verification Infrastructure for IP to SoC
This is to inform you that the next DVClub Europe meeting takes place on Tuesday 05th September with a theme of “Cache Coherency Verification”. SoC cache coherency verification is one of the most complex challenges faced by verification… DVClub Europe – Cache Coherency Verification
Best Conference Papers from 2022 These papers are selected from DVCon and CadenceLive! in 2022 as being most relevant to the DVClub Europe community. Agenda (GMT) 12:00 Welcome and Introduction – Mike Bartley, Tessolve 12:00 Lukas… DVClub Europe – Best Conference Papers from 2022
cocotb is an open source coroutine-based cosimulation testbench environment for verifying VHDL and SystemVerilog RTL using Python. cocotb connects a testbench written in Python with almost all industry-standard simulators. Additionally, cocotb provides a small but… DVClub Europe: Make Verification Fun Again with Python and cocotb
With the popularity of the RISC-V open architecture, many companies are looking for Verification Strategies for developing their own cores or how to verify their integration into a subsystem or SoC. Time Session Description Slides… RISC-V Verification Strategies