FPGAs have made a regular evolutional leap forward in terms of new approaches and solutions for both hardware- and software developers. The FPGA Conference Europe, organized by ELEKTRONIKPRAXIS and the FPGA training center PLC2, is… FPGA-Conference Europe
PCIe-based FPGA designs are becoming popular within avionics systems. However, the verification of such designs for DO-254 compliance with design assurance level (DAL) A or B is problematic. FPGA designs that use asynchronous clocks with… Verification of PCIe-based FPGA Designs Requiring DO-254 Compliance (US)
Join Achronix for a live Webinar December 16th: 10-11 AM Pacific and Recorded On-Demand After the Event AI/ML hardware faces three common pain points: memory bandwidth, computational throughput and on-chip data movement. Next-generation FPGA technology… How to Overcome the Pain Points of AI/ML Hardware Design
Abstract: Today’s FPGAs and SoC FPGAs use various types of bus interconnect – such as AXI, APB, AHB, Avalon or Wishbone – for both internal (IP-level) and external communication. A recently added feature to Aldec’s… LIVE WEBINAR: How to Simplify the Verification of Bus Interfaces (US)
We are changing the world through this. So you can! Join the FPGA Hackathon we organize in Kraków to learn more about the technology gaining more and more popularity! Sharing this passion is the reason… FPGA Conference and Hackathon
Presenter: Espen Tallaksen, CEO of EmLogic Thursday, October 14, 2021 Abstract: Cycle related corner cases are probably the worst and main reason for undetected bugs on many FPGAs. To explain this in a simple way,… The most error prone FPGA corner cases
Abstract: Started with an early adaptor release as Accellera 1.0a, UVM has evolved into few significant versions including UVM 1.1 and UVM 1.2. As with many popular useful standards, UVM has attained the coveted IEEE… UVM for FPGAs (Part 4): IEEE 1800.2 UVM Updates
CHIPS Alliance, the open source RTL hardware and software development tool organization, is gathering to share milestones, progress, updates and more.
What is VSDOpen 2021 Agenda? Key strategy – Provide High Tech Experience of developing analog designs using Open-Source Tools, PDKs and Cloud Platform 3 days of Conference Tutorials Key Focus – Analog Products, Open-source FPGA… VSDOpen 2021 Online Conference
Abstract: Today’s FPGAs have become larger in logic density and can handle complex designs with multi-million system logic cells. The traditional verification techniques of simple simulations combined with a detailed validation in the lab simply… UVM for FPGAs (Part 2): Solving FPGA Verification Challenges with UVM