Join us for “RISC-V in… Space” on November 2, 2023, as we explore the exciting intersection of RISC-V, electronics design, and space! Agenda 9:30 AM – 10:00 AM Registration & Welcome 10:00 AM – 12:00 PM Case Study Presentations:… RISC-V in Space
ASIP University Day: Domain-Specific Processor Design using ASIP Designer Application-specific instruction set processors (ASIPs) have established themselves as an important implementation option for modern SoCs, i.e. when standard processor IP cannot meet challenging application-specific requirements,… ASIP University Day 2023
The RISC-V Instruction Set Architecture (ISA) is the future of computing. As an open standard, RISC-V is accelerating innovation and enabling unprecedented design freedom across every computing application. You’ve seen the headlines and stories. Now,… RISC-V 101
The ability to mix and match multiple ISA extensions and add user-defined ISA extensions makes RISC-V verification more challenging than conventional processor verification. This Synopsys webinar demonstrates the verification of standard RISC-V ISA extensions. A… Efficient Bluespec RISC-V Processor Verification for Highest Coverage Closure: A Comprehensive Case Study
Each day, thousands of engineers around the world collaborate and contribute to advance RISC-V, the open-standard instruction set architecture that is defining the future of open computing. The RISC-V community shares the technical investment and… RISC-V Summit US
RTL engineering change order (ECO) is vital to ensuring proper functionality of integrated circuits (ICs). Retiming and auto ungrouping optimize RTL implementation and enhance PPA. However, aggressive optimizations in CPU RTL designs present challenges due… A Novel Approach to Implementing Logical ECOs with Synopsys Formality ECO on High Performance RISC-V Cores
RISC-V SoC design complexity continues to increase and create new verification challenges. Private caches, shared caches, and shared main memory create potential caches/memory coherency problems that require modern, automated verification approaches. In this webinar, we’ll… Automated Verification for Cache Coherent RISC-V SoCs
RISC-V Day Tokyo 2023 Summer Conference is Japan’s largest RISC-V real event. RISC-V Day Tokyo 2023 Summer Conference will be held on June 20, 2023 (Tuesday) from 9:00 to 20:30 Japan time (JST). A real… RISC-V Days Tokyo 2023 Summer
RISC-V is revolutionizing the future of Artificial Intelligence (AI) in industries such as automotive, data center, communications, and IoT. Its open-source instruction set architecture (ISA) provides higher performance, lower power, and compact silicon footprint, features… 2023 Andes RISC-V CON
IP vendor SiFive has been at the forefront of RISC-V’s rapidly growing adoption across a wide array of markets and applications. In this joint presentation with Ansys, SiFive will describe how achieving maximum compute density… SiFive Maximizes Compute Density With Its RISC-V Processor Cores