The growth of semiconductor industry hinges on the fact that with every new generation, chips would have higher performance and consume less power. However, we… Read More »Design Methodology for Building Power Efficient RTL
Want to take a tour of this powerful power estimation tool and gear up so you understand the Joules flow? Join Cadence Training and Sr… Read More »Introduction to the Joules RTL Power Solution
Abstract: In a team environment, verification engineers push code changes every day, and sometimes several times a day, to a shared repository. Each change has… Read More »Increase your productivity with Continuous Integration flows
Exploring the impact of RTL on implementation PPA has traditionally been very difficult since it was hard to connect the results to the source code. The… Read More »Improving Design Power and Performance with RTL Architect
Verifying changes to RTL and testbench code prior to releasing to the rest of your team is the best way to avoid committing bugs that… Read More »Practical Flows for Continuous Integration: Making The Most of Your EDA Tools
CHIPS Alliance, the open source RTL hardware and software development tool organization, is gathering to share milestones, progress, updates and more.
Learn how UVM Register Access Layer (RAL) can help Presenter: Srinivasan Venkataramanan, Entrepreneur and Head of VerifWorks Thursday, September 23, 2021 Abstract: The use of… Read More »UVM for FPGAs (Part 3): Verifying Zynq MPSoC Designs?
Low power is an increasingly critical requirement for all modern SoCs. Moreover, it is becoming more and more difficult with complex architectures being used in modern designs. This has made… Read More »Pre-empt Late-stage Low Power Issues using Predictive Analysis