ASIC Design Using OpenROAD
Join us for a free, half-day workshop on the key concepts of an ASIC design physical implementation flow using OpenROAD. OpenROAD delivers a fast, barrier-free, and low-cost… Read More »ASIC Design Using OpenROAD
RTL
Low-Power Verification Using Xcelium Simulation
Don’t let power-related issues that appear late in the verification cycle impact your project schedule. Register for a webinar that shows you how to catch… Read More »Low-Power Verification Using Xcelium Simulation
From MATLAB to Optimized RTL in Minutes
As semiconductor process technology advances, predicting and achieving design power, performance, and area (PPA) goals become increasingly difficult. Developing high-performance algorithms for AI and signal… Read More »From MATLAB to Optimized RTL in Minutes
Forum on Specification and Design Languages
FDL is a well-established international forum to exchange experiences and promote new trends in the application of languages, their associated design methods, and tools for… Read More »Forum on Specification and Design Languages
Design Methodology for Building Power Efficient RTL
The growth of semiconductor industry hinges on the fact that with every new generation, chips would have higher performance and consume less power. However, we… Read More »Design Methodology for Building Power Efficient RTL
Introduction to the Joules RTL Power Solution
Want to take a tour of this powerful power estimation tool and gear up so you understand the Joules flow? Join Cadence Training and Sr… Read More »Introduction to the Joules RTL Power Solution
Increase your productivity with Continuous Integration flows
Abstract: In a team environment, verification engineers push code changes every day, and sometimes several times a day, to a shared repository. Each change has… Read More »Increase your productivity with Continuous Integration flows
Improving Design Power and Performance with RTL Architect
Exploring the impact of RTL on implementation PPA has traditionally been very difficult since it was hard to connect the results to the source code. The… Read More »Improving Design Power and Performance with RTL Architect
Practical Flows for Continuous Integration: Making The Most of Your EDA Tools
Verifying changes to RTL and testbench code prior to releasing to the rest of your team is the best way to avoid committing bugs that… Read More »Practical Flows for Continuous Integration: Making The Most of Your EDA Tools
FPGA Conference and Hackathon
We are changing the world through this. So you can! Join the FPGA Hackathon we organize in Kraków to learn more about the technology gaining… Read More »FPGA Conference and Hackathon