UVM for FPGAs (Part 3): Verifying Zynq MPSoC Designs?

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Learn how UVM Register Access Layer (RAL) can help Presenter: Srinivasan Venkataramanan, Entrepreneur and Head of VerifWorks Thursday, September 23, 2021 Abstract: The use of highly configurable IP-based designs have become the norm in the SoC era. Modern SoC designs … Continued

Improving Initial RTL Quality

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Development projects, whether FPGA or ASIC SoCs or IP, run into late surprises that quickly result in schedule slips, expensive rework, and/or difficult feature cuts. It is possible to find entire classes of issues without waiting for a testbench. This … Continued

Pre-empt Late-stage Low Power Issues using Predictive Analysis

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Low power is an increasingly critical requirement for all modern SoCs. Moreover, it is becoming more and more difficult with complex architectures being used in modern designs. This has made it necessary for designers to invest heavily in this verification effort throughout the design development cycle starting … Continued

Transcending RTL – At DAC This Year

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I first met Steve Hoover a few years ago online, then at a DAC. We both worked at Intel, so his startup company Redwood EDA caught my attention. I’ve watched over the decades as Verilog and VHDL grew up to … Continued