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Aldec, January 20, 2022

Increase your productivity with Continuous Integration flows

Abstract: In a team environment, verification engineers push code changes every day, and sometimes several times a day, to a shared repository. Each change has… Read More »Increase your productivity with Continuous Integration flows

Siemens EDA, November 16

Practical Flows for Continuous Integration: Making The Most of Your EDA Tools

Verifying changes to RTL and testbench code prior to releasing to the rest of your team is the best way to avoid committing bugs that… Read More »Practical Flows for Continuous Integration: Making The Most of Your EDA Tools

Sep 23 Aldec

UVM for FPGAs (Part 3): Verifying Zynq MPSoC Designs?

Learn how UVM Register Access Layer (RAL) can help Presenter: Srinivasan Venkataramanan, Entrepreneur and Head of VerifWorks Thursday, September 23, 2021 Abstract: The use of… Read More »UVM for FPGAs (Part 3): Verifying Zynq MPSoC Designs?

Synopsys Webinar

Pre-empt Late-stage Low Power Issues using Predictive Analysis

Low power is an increasingly critical requirement for all modern SoCs. Moreover, it is becoming more and more difficult with complex architectures being used in modern designs. This has made… Read More »Pre-empt Late-stage Low Power Issues using Predictive Analysis

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