Don’t let power-related issues that appear late in the verification cycle impact your project schedule. Register for a webinar that shows you how to catch low-power issues early on. The Cadence low-power solution considers power… Low-Power Verification Using Xcelium Simulation
As semiconductor process technology advances, predicting and achieving design power, performance, and area (PPA) goals become increasingly difficult. Developing high-performance algorithms for AI and signal processing is particularly challenging as algorithm development is abstracted from… From MATLAB to Optimized RTL in Minutes
FDL is a well-established international forum to exchange experiences and promote new trends in the application of languages, their associated design methods, and tools for the design of electronic systems. FDL stimulates scientific and controversial… Forum on Specification and Design Languages
The growth of semiconductor industry hinges on the fact that with every new generation, chips would have higher performance and consume less power. However, we are witnessing that scaling through Moore’s law does not automatically… Design Methodology for Building Power Efficient RTL
Want to take a tour of this powerful power estimation tool and gear up so you understand the Joules flow? Join Cadence Training and Sr Principal Education Application Engineer Neha Joshi for this free technical… Introduction to the Joules RTL Power Solution
Abstract: In a team environment, verification engineers push code changes every day, and sometimes several times a day, to a shared repository. Each change has the potential to introduce new bugs into the design. Accordingly,… Increase your productivity with Continuous Integration flows
Exploring the impact of RTL on implementation PPA has traditionally been very difficult since it was hard to connect the results to the source code. The first difficulty occurs during elaboration and synthesis. The RTL is… Improving Design Power and Performance with RTL Architect
Verifying changes to RTL and testbench code prior to releasing to the rest of your team is the best way to avoid committing bugs that cause massive, team-wide disruptions. This webinar takes you through example… Practical Flows for Continuous Integration: Making The Most of Your EDA Tools
We are changing the world through this. So you can! Join the FPGA Hackathon we organize in Kraków to learn more about the technology gaining more and more popularity! Sharing this passion is the reason… FPGA Conference and Hackathon
CHIPS Alliance, the open source RTL hardware and software development tool organization, is gathering to share milestones, progress, updates and more.