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Cadence, January 25, 2023

Low-Power Verification Using Xcelium Simulation

Don’t let power-related issues that appear late in the verification cycle impact your project schedule. Register for a webinar that shows you how to catch low-power issues early on. The Cadence low-power solution considers power… Low-Power Verification Using Xcelium Simulation

Cadence, September 22, 2022

From MATLAB to Optimized RTL in Minutes

As semiconductor process technology advances, predicting and achieving design power, performance, and area (PPA) goals become increasingly difficult. Developing high-performance algorithms for AI and signal processing is particularly challenging as algorithm development is abstracted from… From MATLAB to Optimized RTL in Minutes

FDL 2022

Forum on Specification and Design Languages

FDL is a well-established international forum to exchange experiences and promote new trends in the application of languages, their associated design methods, and tools for the design of electronic systems. FDL stimulates scientific and controversial… Forum on Specification and Design Languages

Siemens EDA, April 12, 2022

Design Methodology for Building Power Efficient RTL

The growth of semiconductor industry hinges on the fact that with every new generation, chips would have higher performance and consume less power. However, we are witnessing that scaling through Moore’s law does not automatically… Design Methodology for Building Power Efficient RTL

Joules, March 8, 2022

Introduction to the Joules RTL Power Solution

Want to take a tour of this powerful power estimation tool and gear up so you understand the Joules flow? Join Cadence Training and Sr Principal Education Application Engineer Neha Joshi for this free technical… Introduction to the Joules RTL Power Solution

Aldec, January 20, 2022

Increase your productivity with Continuous Integration flows

Abstract: In a team environment, verification engineers push code changes every day, and sometimes several times a day, to a shared repository. Each change has the potential to introduce new bugs into the design. Accordingly,… Increase your productivity with Continuous Integration flows

Improving Design Power and Performance with RTL Architect

Exploring the impact of RTL on implementation PPA has traditionally been very difficult since it was hard to connect the results to the source code.  The first difficulty occurs during elaboration and synthesis. The RTL is… Improving Design Power and Performance with RTL Architect

Siemens EDA, November 16

Practical Flows for Continuous Integration: Making The Most of Your EDA Tools

Verifying changes to RTL and testbench code prior to releasing to the rest of your team is the best way to avoid committing bugs that cause massive, team-wide disruptions. This webinar takes you through example… Practical Flows for Continuous Integration: Making The Most of Your EDA Tools