RTL-to-GDSII Flow for ASIC Design Using Cadence Tools

Would you like to know how to design a complete chip using the RTL-to-GDSII Flow?

In this free technical Training Webinar with Application Engineer Sai Srinivas Pamula, we’ll teach you the essential steps in the RTL-to-GDSII design flow using a wide variety of industry-leading Cadence tools—such as the Xcelium Logic Simulator, Modus DFT Software Solution, Genus Synthesis Solution, Conformal technologies, Innovus Implementation System, and Tempus Timing Solution—that provide great power, performance, and area (PPA).

We’ll explore topics like:

• Writing RTL code using Verilog or VHDL
• Synthesizing the RTL design into a gate-level netlist
• Inserting scan chains into the netlist for testing and debugging
• Performing logic equivalence checking to verify that the synthesized design is functionally equivalent to the original RTL design
• Implementing the netlist by performing floorplanning, placement, clock tree synthesis, and routing
• Performing timing signoff to verify that the design meets all of its timing requirements
• Extracting the GDSII file from the physical layout to manufacture the chip

Webinar
RTL-to-GDSII Flow for ASIC Design Using Cadence Tools

Date and Time
Wednesday, December 13
07:00 PST San Jose / 10:00 EST New York / 15:00 GMT London / 16:00 CET Berlin / 17:00 IST Jerusalem / 20:30 IST Bangalore / 23:00 CST Beijing

To register for the RTL-to-GDSII Flow for ASIC Design Using Cadence Tools webinar, sign in with your Cadence Support account (email ID and password) to log in to the Learning and Support System. Then select Enroll to register for the session. Once registered, you’ll receive a confirmation email containing all login details. If you don’t have a Cadence Support account, go to Registration Help or Cadence User Registration and complete the requested information.