If you can’t make the live session, please register anyway and you’ll get the link to the recorded session afterward. The complicated silicon defect types and defect distribution for advanced technologies can lead to initially very low…
The Design and Verification Conference in Europe (DVCon Europe) is the leading European event covering the application of languages, tools and intellectual property for the design and verification of electronic systems and integrated circuits. Sponsored…
Development projects, whether FPGA or ASIC SoCs or IP, run into late surprises that quickly result in schedule slips, expensive rework, and/or difficult feature cuts. It is possible to find entire classes of issues without…
Agenda (BST): Time Session Description Slides Videos 12.00 BST 16:30 IST Welcome and Introduction Mike Bartley, Senior Vice President – VLSI Design, Tessolve 12.05…
We’re already into the new year, so it was about time that I updated my list of Semi and EDA vendors that I’ve blogged or consulted for, here’s what changed: Mentor became Siemens EDA Moortec…