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DVClub Europe
September 7, 2021 @ 12:00 pm - 1:30 pm BST
Agenda (BST):
| Time | Session Description | Slides | Videos | |
| 12.00 BST 16:30 IST | Welcome and Introduction Mike Bartley, Senior Vice President – VLSI Design, Tessolve |
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| 12.05 BST 16:35 IST | I’m Excited About Formal…My Journey From Skeptic To Believer Neil Johnson, Senior Product Engineering Manager, Siemens EDA |
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| 12.30 BST 17:00 IST | Formal Verification Adoption Made Easy Alexandre Esselin Botelho, Sr. Principal Application Engineer, Cadence Design System |
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| 12.55 BST 17:25 IST | Formal for Easing the SystemC/C++ Verification Burden Vlada Kalinic, Product Specialist (for SystemC), OneSpin A Siemens Business |
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| 13.20 BST 17:50 IST | Closing Remarks | |||
| 13.30 BST 18:00 IST | Close |