DVCon Europe 2021

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The Design and Verification Conference in Europe (DVCon Europe) is the leading European event covering the application of languages, tools and intellectual property for the design and verification of electronic systems and integrated circuits. Sponsored by Accellera Systems Initiative, DVCon … Continued

Formal 101 – Exhaustive Scoreboarding and Data Integrity Verification Made Easy

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Verifying the correct passage of data through a DUT in constrained-random simulation is easy to do for basic I/O cases – data loss, obvious corruption, and 1-1 data passage. But what about verifying out-of-order cases? Or intermittently dropped bytes? Granted, … Continued

A Novel Reversible Scan Chain Technology that Improves Chain Diagnosis Resolution by 4X

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If you can’t make the live session, please register anyway and you’ll get the link to the recorded session afterward. The complicated silicon defect types and defect distribution for advanced technologies can lead to initially very low yield for new design with … Continued

Improving Initial RTL Quality

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Development projects, whether FPGA or ASIC SoCs or IP, run into late surprises that quickly result in schedule slips, expensive rework, and/or difficult feature cuts. It is possible to find entire classes of issues without waiting for a testbench. This … Continued

DVClub Europe

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Agenda (BST): Time Session Description           Slides              Videos 12.00 BST 16:30 IST Welcome and Introduction Mike Bartley, Senior Vice President – VLSI Design, Tessolve 12.05 BST 16:35 IST I’m Excited … Continued

Blog Updates for 2021

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We’re already into the new year, so it was about time that I updated my list of Semi and EDA vendors that I’ve blogged or consulted for, here’s what changed: Mentor became Siemens EDA Moortec acquired by Synopsys Methodics acquired … Continued