Leveraging functional patterns is crucial for achieving high defect coverage and reducing defective parts per million (DPPM) levels. Synopsys VC Z01X fault simulator offers enhanced fault coverage… Read More »Enhancing Manufacturing Test Flows with Synopsys VC Z01X
The comprehensive verification of analog mixed-signal (AMS) designs has challenges in schedules and implementations due to the vast divergence in design flows of the analog… Read More »Enhance Verification Quality with the Xcelium Mixed-Signal App
Although SystemVerilog is perhaps most widely used in the context of hardware verification, it also contains many features directly relevant to FPGA hardware designers. We… Read More »Maximize Design Productivity using Vivado ML with SystemVerilog
This webinar gives a comprehensive guide to all aspects of SystemVerilog arrays: ordinary static arrays, dynamic arrays, queues and associative arrays. It also includes array… Read More »Everything You Need to Know about SystemVerilog Arrays
Xcelium mixed-signal simulation enables teams to achieve digital simulation speeds of analog models and opens mixed-signal designs to advanced verification techniques typically applied within standard… Read More »Xcelium: The Key to Unlocking Unmatched Mixed-Signal Performance
The programming interfaces of logic simulators are largely the domain of specialists writing proprietary tools and extensions and are only vaguely in the consciousness of… Read More »The Power of SystemVerilog’s DPI
The Verification Futures conference provides a unique blend of conference presentations, exhibitions, training and industry networking sessions dedicated to discussing the challenges faced in hardware… Read More »Verification Futures 2023 UK
Sigasi Studio serves as a code browser for VHDL, Verilog and SystemVerilog. You can navigate through your project to understand large and complex legacy designs.… Read More »Sigasi September Productivity Hacks Workshop
Sigasi Studio serves as a code browser for VHDL, Verilog and SystemVerilog. You can navigate through your project to understand large and complex legacy designs.… Read More »Sigasi September Productivity Hacks Workshop
Learn how to write UVM testbenches for analog/mixed-signal circuits. UVM (Universal Verification Methodology) is a framework of standardized SystemVerilog classes to build reusable and scalable… Read More »Writing UVM/SystemVerilog Testbenches for Analog/Mixed-Signal Verification