As traditional Moore’s law scaling approaches its physical limits, the industry is moving towards multi-die solutions for higher electronics system densities. Multi-die designs present one… Read More »Step-by-Step Guide for Your UCIe Design Verification
Why Attend Flash Memory Summit? Flash Memory Summit (FMS) is an all-inclusive international memory and storage showcase. It is the event for the memory and… Read More »Flash Memory Summit
Chiplets are emerging as a new way of building IC systems via heterogeneous integration, and Universal Chip Interconnect Express (UCIe) is one of the standards… Read More »UCIe PHY Modeling and Simulation with XMODEL
Wednesday, May 24, 2023 and Thursday, May 25, 2023 The industry is moving to multi-die systems to benefit from the greater compute performance, increased functionality,… Read More »Requirements for Multi-Die System Success
UCIe™ — Universal Chiplet Interconnect Express™ — is an open industry standard founded by the leaders in semiconductors, packaging, IP suppliers, foundries, and cloud service… Read More »Introduction to UCIe
I had the pleasure to attend the SEMI event held November 2nd in Beaverton, Oregon, just a few miles away from where I live in… Read More »SEMI: The Future of More than Moore
Multi-die architectures have evolved from proprietary to industry standard UCIe. UCIe can accommodate the bulk of designs today from 8 Gbps per pin to 32… Read More »Evaluating UCIe based multi-die architectures to meet timing and power constraints
The First Annual Chiplet Summit is the show chip designers can’t miss if they want to stay competitive. They’ll get the scoop on ways to… Read More »Chiplet Summit
Emerging 2.5D and 3DIC packaging technologies enable more design complexity, and bring some new verification challenges. We look at how to scale your verification capability… Read More »Protocol and Memory Interface Verification in the Shrinking World of 3DIC