Future of Memory and Storage – 2024
FMS: the Future of Memory and Storage is an all-inclusive international memory and storage showcase. It is the event for the memory and storage industry. It… Read More »Future of Memory and Storage – 2024
UCIe
Optimizing Chiplet architectures of RISC-V clusters, GPU and DNN using System-Level IP
Multi-die SoC containing multiple RISC-V clusters, GPU, NPU, accelerators and DNN have considerable benefits for applications in automotive, space and industrial. Architecture exploration of the… Read More »Optimizing Chiplet architectures of RISC-V clusters, GPU and DNN using System-Level IP
Optimizing Chiplet architectures of RISC-V clusters, GPU and DNN using System-Level IP
Multi-die SoC containing multiple RISC-V clusters, GPU, NPU, accelerators and DNN have considerable benefits for applications in automotive, space and industrial. Architecture exploration of the… Read More »Optimizing Chiplet architectures of RISC-V clusters, GPU and DNN using System-Level IP
Exploring the Advancement of Chiplet Technology and the Ecosystem
Semiconductor companies are making transistors smaller and cramming more into chips to meet the demands of today’s high-tech industries and applications. In fact, in a recent… Read More »Exploring the Advancement of Chiplet Technology and the Ecosystem
Multi-Die System Verification with Siemens Avery UCIe VIP
Conventional monolithic SoCs are becoming a bottleneck for power, performance, and area (PPA), creating limitations for Data-intensive applications like high-performance computing (HPC), machine learning (ML)… Read More »Multi-Die System Verification with Siemens Avery UCIe VIP
Why Chiplets with UCIe are the Next Big Thing
Artificial intelligence (AI) and virtual reality (VR) require fast, efficient, low-power technologies. Transistors are becoming harder and harder to shrink, so chiplets are a promising alternative. Chiplets are small, modular… Read More »Why Chiplets with UCIe are the Next Big Thing
Unleashing Innovation with UCIe
Exploring the Next Frontier in Chip Integration Webinar Agenda : Introduction to all UCIe layers Decrypting FLITs, PHY Trainings, Bring up flows FDI-RDI , main… Read More »Unleashing Innovation with UCIe
The UCIe™ 1.1 Specification: Future Applications of Chiplets
Presenter: Dr. Debendra Das Sharma, UCIe Consortium Chairman and Intel Senior Fellow, Chief Architect of I/O Technology and Standards at Intel The UCIe™ (Universal Chiplet Interconnect… Read More »The UCIe™ 1.1 Specification: Future Applications of Chiplets
UCIe-Based Chiplet Verification – from IP to SoC
Innovative die disaggregation technologies, enable a future where a catalog of chiplets will be available to mix and match based on the end application. The… Read More »UCIe-Based Chiplet Verification – from IP to SoC
UCIe-Based Chiplet Verification – from IP to SoC
Innovative die disaggregation technologies, enable a future where a catalog of chiplets will be available to mix and match based on the end application. The… Read More »UCIe-Based Chiplet Verification – from IP to SoC