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UCIe

Mirabilis, October 27, 2022

Evaluating UCIe based multi-die architectures to meet timing and power constraints

Multi-die architectures have evolved from proprietary to industry standard UCIe.  UCIe can accommodate the bulk of designs today from 8 Gbps per pin to 32… Read More »Evaluating UCIe based multi-die architectures to meet timing and power constraints

Siemens EDA

Protocol and Memory Interface Verification in the Shrinking World of 3DIC

Emerging 2.5D and 3DIC packaging technologies enable more design complexity, and bring some new verification challenges. We look at how to scale your verification capability… Read More »Protocol and Memory Interface Verification in the Shrinking World of 3DIC

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