At Veriest, we believe in knowledge sharing. In our recent meetup events, hundreds of professionals from 20+ different countries gathered to listen to different industry… Read More »Veriest – Verification Meetup in Budapest
Traditional coverage-based verification methods are no longer sufficient to verify complex SoCs integrating many processor cores and IP subsystems. To conquer the verification challenge of… Read More »Exploring a Software First Approach to Avoid SoC Re-spins
Overview Low power DRAM is being adopted in a wide array of markets, including automotive, PCs and networking systems built for 5G and AI applications.… Read More »Boost LPDDR5 Verification from IP to System Level
Open Verification Library (OVL) is a library of property checkers for digital circuit descriptions written in popular Hardware Description Languages and maintained by Accelera. The… Read More »Using OVL for Assertion-based Verification of Verilog and VHDL Designs
Veriest is inviting you to another event in our series of online Verification Meetups. This time, we’ll have two presentations on the polemic topic of… Read More »Python in Verification Online Meetup
Development projects, whether FPGA or ASIC SoCs or IP, run into late surprises that quickly result in schedule slips, expensive rework, and/or difficult feature cuts.… Read More »Improving Initial RTL Quality