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3DIC Design from Concept to Silicon
February 10 @ 10:00 am - 11:00 am PST
For some high-performance computing (HPC) designs, monolithic SoCs aren’t producing the scalability and yield that designers are looking for. New trends towards 3DIC design are emerging introducing new design challenges, such as reliable die-to-die connectivity, high bandwidth memory, integration, and 2.5D or 3D packaging options. This webinar will outline the different market trends for 3DIC designs and explain how designers can maintain such new trends to deliver their designs with optimized latency, power, performance, and area. We will also demonstrate the construction of a 3DIC design and our 3rd generation HBM interposer auto-routing solution.
Learn about considerations and trends for a more efficient 3DIC design integration Find out how protocols like HBM3 and Die-to-Die are influencing 3DIC designs See a demo of a 3DIC design construction
Kenneth Larsen is a product marketing director in the Silicon Realization Group at Synopsys. He is a versatile leader with a strong background in defining and executing product vision, marketing strategy, inspiring product development teams, translating technology concepts into customer solutions, developing high-performance global organizations, conceiving and driving new and emerging products to scale from the ground up, guiding marketing, and enabling sales. Kenneth has a degree in electrical engineering and additional coursework in strategic growth at Columbia Business School, and Artificial Intelligence at MIT Sloan School of Management.
Eric Means is an Applications Engineer in Hillsboro, Oregon supporting Synopsys 3DIC Compiler users. He has worked with ASIC and EDA customers for 25 years at NEC, Renesas, & Synopsys. He has a BS in Electrical Engineering from Washington State University and an MS in Computer Engineering from the Oregon Graduate Institute.
*This webinar is in partnership with SemiWiki and Synopsys*