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CXL and IDE: Important Considerations of Protecting High Speed Interconnects

November 9 @ 10:00 am - 11:00 am PST

rambus siemens

In a few short years, CXL (Compute Express Link) has evolved from an idea to a rapidly proliferating low latency interconnect standard being adopted into data centers, high performance computing, and cloud computing. However, as the adoption has increased, so has the security threat model users face. To address this, the CXL 2.0 standard has included an optional IDE (Integrity and Data Encryption). While IDE is optional today, given ever-increasing security threats, it won’t be forever so understanding IDE will become essential.

In this webinar, Rambus and Siemens will discuss the background of IDE, the threat models it addresses, and how zero latency IDE’s can provide assurances to CXL adopters. Design and verification engineers and managers won’t want to miss this webinar to understand how to incorporate and validate this essential standard in their designs.

Speakers

Allan Gordan, Siemens EDA
Product Manager for Verification IP

Arjun Bangre, Rabus
Director of Product Management for PCIe and CXL controllers

Details

Date:
November 9
Time:
10:00 am - 11:00 am PST
Event Categories:
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Event Tags:
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Event Website

Organizer

Siemens EDA
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