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International Workshop on Logic and Synthesis – IWLS 2024
June 6 @ 8:00 am - June 7 @ 5:00 pm CEST
The International Workshop on Logic and Synthesis is the premier forum for research in synthesis, optimization, and verification of integrated circuits and systems. Research on logic synthesis for emerging technologies and for novel computing platforms, such as nanoscale systems and biological systems, is also strongly encouraged. The workshop encourages the early dissemination of ideas and results. The workshop accepts complete papers highlighting important new problems in the early stages of development, without providing complete solutions. The emphasis is on novelty and intellectual rigor.
Topics of interest include but are not limited to: hardware synthesis and optimization; software synthesis; hardware/software co-synthesis; power and timing analysis; testing, validation, and verification; synthesis for reconfigurable architectures; hardware compilation for domain-specific languages; and design experiences. Submissions on modeling, analysis, and synthesis for emerging technologies and platforms are particularly encouraged.
The workshop format includes paper presentations, invited talks, social lunch and dinner gatherings, and recreational activities.
Check out our call for papers.
Keynotes
Can AI Design and Verify Your Design?
Ziyad Hanna, Cadence Design Systems, Israel
Abstract: In this talk, I will explore the significant impact of artificial intelligence (AI) in addressing the mounting complexity and demands within chip design domain. With an anticipated exponential growth in annual revenue reaching the trillion-dollar mark, driven by the rapid growth in key markets in 5G, Hyperscalers, autonomous vehicles, AI, and industrial IoT. The chip design market is trending into a fourfold increase in project volume with tenfold complexity. The current design and verification methodologies are lacking in capacity to meet this surge, highlighting the shortage of qualified engineers to meet the aggressive market demand. AI technologies stand at the forefront of transforming design and verification processes, offering unparalleled efficiency and cost-effective solutions to meet the escalating market needs. In this talk, I will address the inherent challenges in the chip design industry, analyze the current landscape of automation, machine learning (ML), and cutting-edge generative AI technologies. I will also discuss a strategic direction for harnessing AI to enhance design synthesis and verification, including the automatic generation of programs supported by natural language processing (NLP) and generative AI, the creation of temporal assertions from design specifications, the integration of high-level synthesis (HLS) and formal verification, and the exploration of the latest advancements in AI technologies for full design and verification flow for achieving the aggressive demand on performance, power and area. Furthermore, the presentation emphasizes the essence for collaborative initiatives between industry and academia to drive forward transformative advancements and innovations within the chip design and verification domain with AI.
Ziyad Hanna, Ph.D., is currently a corporate VP at Cadence Design Systems (CDNS), and the general manager of Cadence Israel, leading R&D centers in various countries, in the electronic design automation domain. Prior to joining Cadence Design Systems, Dr. Hanna was a Senior VP at Jasper Design Automation, which was acquired by Cadence in 2014. At Jasper, Dr. Hanna worked in the fast-emerging domain of formal verification technology and applications. Dr. Hanna was also an Intel Senior Principal Engineer and R&D Group Leader at Intel Haifa, where he was instrumental in the development of several generations of formal verification systems, which were used on almost all Intel microprocessor designs since early 1990s, and was twice the recipient of Intel’s highest Achievement Award (IAA). He received both his BS and MS degrees in Computer Science at Tel Aviv University, and his PhD in Computer Science from the University of Oxford. Besides his leadership at Cadence, Prof. Hanna is currently serving as a visiting professor of Computer Science at Oxford. Dr. Hanna is a senior IEEE member, holds over 15 patents, and has published more than 80 papers and talks.
Symmetric Is Better: Can We Exploit Regularities in Logic Synthesis?
Valentina Ciriani, University of Milano, Italy
Abstract: The standard synthesis of Boolean functions is aimed at designing optimized circuits according to given cost criteria. For this purpose, the algebraic form of the function is manipulated, as it directly reflects the cost of the corresponding circuit. Depending on the design needs, different two-level or multi-level forms are considered, and ad hoc algorithms are used to express and minimize such forms. In all cases, the functions under consideration encode “real life” problems, hence they often exhibit a “regular” structure that can be exploited by synthesis algorithms. This talk aims to describe several function regularities based on the EXOR operator. Moreover, we show how these regularities can be exploited in logic synthesis for standard and emerging technologies. Finally, we show how regularities can also ease polynomial verification.
Valentina Ciriani received the Laurea degree and the Ph.D. degree in Computer Science from the University of Pisa, Italy, in 1998 and 2003, respectively. In 2003 and 2004 she was with the Department Computer Science at University Pisa, Italy as a Ph.D. fellow. From 2005 to 2015 she was an assistant professor in Computer Science at the Department of Computer Science, University of Milano, Italy. She is currently an Associate Professor in Computer Science with the Department of Computer Science of the University of Milano (Italy). Her research interests include algorithms and data structures, as well as combinational logic synthesis for classical and emerging technologies. She has authored or coauthored more than 100 research papers, published in international journals, conference proceedings, and books chapters.
Toward Software-to-Atoms Open-Source RISC-V Computing Platforms: Is Open-Source Synthesis Ready for Prime Time?
Luca Benini, ETH Zurich / University of Bologna, Switzerland / Italy
Abstract: The success of the RISC-V free and open ISA has ushered us in the era Open-source computing hardware. As of today, open-source designs exist targeting a wide range of RISC-V based computing systems, from tiny microcontrollers to high-performance many-core, and industry adoption of open-source computing hardware is accelerating. However a key open question is if we can, or even should, push further, open sourcing design automation tools and technology libraries, PDKs, toward the vision of enabling “software-to-atoms” open source computing platforms. In this talk I will try assess where we stand and provide a personal view on key challenges and future trajectories, drawing from a decade of experience in designing and industrializing open source hardware.
Luca Benini holds the chair of digital Circuits and systems at ETHZ and is Full Professor at the Universita di Bologna. He received a PhD from Stanford University. Dr. Benini’s research interests are in energy-efficient parallel computing systems, smart sensing micro-systems and machine learning hardware. He is a Fellow of the IEEE, of the ACM and a member of the Academia Europaea. He is the recipient of the 2016 IEEE CAS Mac Van Valkenburg award, the 2020 EDAA achievement Award, the 2020 ACM/IEEE A. Richard Newton Award and the 2023 IEEE CS E.J. McCluskey Award.