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Three Issues Every EE Needs to Overcome to Sign Off on High-Speed PCB Designs
November 15 @ 8:00 am - 9:00 am PST
Signal integrity/power integrity (SI/PI) are top priorities for engineers designing today’s high-speed, high-density circuit boards. Faster signoff of designs can be achieved by uncovering signal SI/PI issues early in the design process. This webinar will highlight three key issues engineers need to overcome to sign off on high-speed PCB designs: serial link compliance (SerDes), power analysis, and memory interface (DDR) compliance and how the Cadence PCB design methodology empowers EEs to create successful products on time and on budget.
Nitin Bhagwath is a director of product management at Cadence. Before joining Cadence, he was a product manager at Mentor Graphics for 10 years specializing in signal integrity/power integrity (SI/PI) simulation. He previously designed and architected high-speed systems for Hewlett Packard and Cisco for 10 years. Nitin holds a BSEE from Bangalore University, an MS in civil and environmental engineering from Purdue University, and an MBA from the Indian Institute of Management, Bangalore.
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