EDA
Debugging SystemC with GDB
Webinar Overview: This webinar explores debugging SystemC code with basic tools, including issues and strategies to make improvements. A large portion of the webinar includes a demonstration of a small design. Topics include single-stepping without getting lost and obtaining information about SystemC simulation status. The session concludes with ideas on how to simplify debugging and… Read More »Debugging SystemC with GDB
VLSID 2024
ITC Royal Bengal Kolkata, IndiaThe 37th International Conference on VLSI Design & the 23rd International Conference on Embedded Systems (VLSID 2024) are being held at Kolkata, India, during January 6-10, 2024. VLSID 2024 is returning to the city after 8 years since 2016. This flagship conference is bringing worldwide industry leaders, Indian and international industry bodies, and academic researchers in a… Read More »VLSID 2024
Speed Up Your Electronic Component Design with HPC
About this Webinar Electronic components design and their integration on PCBs involve complex simulations to predict EM fields and forces accurately. These simulations can be computationally intensive and time-consuming. High-Performance Computing (HPC) capability built into Ansys Maxwell core technology significantly accelerates the electronic component design process, enabling quick iteration, optimization, and validation. The ECAD capability… Read More »Speed Up Your Electronic Component Design with HPC
PCB Design Best Practices: How to fully verify your Serdes-based designs before prototype manufacture
“Right first time” is a goal we all aspire to, but how often does it really happen? Even when we follow layout rules as closely as possible, problems creep into the layout that cause issues during lab testing and result in costly, time-consuming respins. Join our expert presenter Todd Westerhoff in this LinkedIn Live… Read More »PCB Design Best Practices: How to fully verify your Serdes-based designs before prototype manufacture
Meet Advanced IC Package Design Schedule Challenges with In-Design Analysis
The heterogeneous integration of chips/chiplets has added significant complexity to the IC package design process, further compressing schedules for many design teams. Design teams must work more efficiently to meet quality and performance goals while maintaining schedule milestones. One way to improve efficiency is to shift signal and power integrity (SI/PI) analysis to earlier in… Read More »Meet Advanced IC Package Design Schedule Challenges with In-Design Analysis
ASP-DAC 2024
Incheon Songdo Convensia 123 Central Street, Yeonsu-gu, Incheon, Korea, Democratic People's Republic ofASP-DAC 2024 is the 29th annual international conference on VLSI design automation in Asia and South Pacific regions, one of the most active regions of design, CAD and fabrication of silicon chips in the world. The conference aims at providing the Asian and South Pacific CAD/DA and Design community with opportunities of presenting recent advances… Read More »ASP-DAC 2024
Verisium SimAI: Coverage Gaps Meet Their Match
Every project has some areas that seem impossible to cover. Various factors can cause these nearly impossible-to-hit coverage gaps, including technical complexity, lack of resources, and shifting requirements. In constrained random environments, simply running more random seeds may not always address these coverage gaps effectively. Overcoming these gaps requires creativity, persistence, and technical expertise. A… Read More »Verisium SimAI: Coverage Gaps Meet Their Match
Automotive World 2024
Tokyo Big Sight 3 Choe-11-1 Ariake, Tokyo, JapanCombination of exhibitions & conferences covering important topics in the automotive industry such as automotive electronics, connected car, autonomous driving, EV/HV/FCV, lightweight, processing technology and MaaS. Automotive OEMs and Tier 1 suppliers visit the exhibition to find suppliers and partners. 1,650 Exhibitors 85,000 Visitors 170 Speakers
Introducing OrCAD X, Our Next-Generation PCB Layout Solution
Whether you’re a beginner or a seasoned engineer, this webinar is a must-watch for anyone in the electronic design space. Join us to discuss how you can accelerate your PCB design process with our new and improved OrCAD X layout environment. Learn how you can: Design with an intuitive UI Collaborate using design review and markup… Read More »Introducing OrCAD X, Our Next-Generation PCB Layout Solution
Validating Clarity 3D Solver Accuracy Through Measurement Correlation
Cadence’s Clarity 3D Solver is an industry-leading EM simulation platform used by hundreds of design teams to address signal and power integrity (SI/PI) challenges. By solving bigger problems on more efficient compute resources, Clarity 3D Solver users have reimagined what can be done with 3D finite element method (FEM) solver technology. However, EM extraction results to… Read More »Validating Clarity 3D Solver Accuracy Through Measurement Correlation
Verifying AXI Interconnects with ALINT-PRO and Riviera-PRO
AXI has become the most popular internal bus protocol with today’s FPGA and SoC FPGA designs. ALINT-PRO enables FPGA designers to extract, review and statically verify AXI bus interfaces. In addition, ALINT-PRO can assist with automatic generation of test harnesses for dynamic verification. For dynamic verification of AXI interconnects, Aldec provides FPGA vendor-agnostic AXI Bus… Read More »Verifying AXI Interconnects with ALINT-PRO and Riviera-PRO
Signal & Power Integrity Special Interest Group
Hilton Santa Clara 4949 Great America Parkway, Santa Clara, CA, United StatesDear SIPI Engineer, As a member of the engineering community, you are invited to attend Synopsys Signal & Power Integrity Special Interest Group event taking place at Hilton Santa Clara. This event is conveniently located across the street from the DesignCon 2024 Conference allowing you to participate in both. The Synopsys SIPI SIG event will… Read More »Signal & Power Integrity Special Interest Group