IP
RISC-V Instruction Set Architecture: Enhancing Computing Power
*Work email required for registration* Don't miss out on this exclusive opportunity to stay ahead in the rapidly evolving landscape of chip design. Join us for an engaging discussion that… Read More »RISC-V Instruction Set Architecture: Enhancing Computing Power
Siemens EDA User2User Conference
Santa Clara Marriott 2700 Mission College Blvd, Santa Clara, CA, United StatesEngineer a smarter future, faster at Siemens EDA User2User Conference April 3-4, 2024 Santa Clara, CA. Join your colleagues from around the industry for a day of technical sessions, networking,… Read More »Siemens EDA User2User Conference
Embedded World 2024
NürnbergMesse Messezentrum 1, Nurnberg, GermanyThe embedded world Exhibition&Conference provides a global platform and a place to meet for the entire embedded community, including leading experts, key players and industry associations. It offers unprecedented insight… Read More »Embedded World 2024
Exploring the Advancement of Chiplet Technology and the Ecosystem
Semiconductor companies are making transistors smaller and cramming more into chips to meet the demands of today’s high-tech industries and applications. In fact, in a recent article from the Financial Times, technology… Read More »Exploring the Advancement of Chiplet Technology and the Ecosystem
CadenceLIVE Silicon Valley 2024
Santa Clara Convention Center 5001 Great America Parkway, Santa Clara, CA, United StatesJoin us for CadenceLIVE Silicon Valley 2024 on April 17 at the Santa Clara Convention Center. This annual user conference features peer presentations that offer solutions for today’s design challenges… Read More »CadenceLIVE Silicon Valley 2024
Optimizing Chiplet architectures of RISC-V clusters, GPU and DNN using System-Level IP
Multi-die SoC containing multiple RISC-V clusters, GPU, NPU, accelerators and DNN have considerable benefits for applications in automotive, space and industrial. Architecture exploration of the chiplet-based SoC requires multiple interconnect… Read More »Optimizing Chiplet architectures of RISC-V clusters, GPU and DNN using System-Level IP
Optimizing Chiplet architectures of RISC-V clusters, GPU and DNN using System-Level IP
Multi-die SoC containing multiple RISC-V clusters, GPU, NPU, accelerators and DNN have considerable benefits for applications in automotive, space and industrial. Architecture exploration of the chiplet-based SoC requires multiple interconnect… Read More »Optimizing Chiplet architectures of RISC-V clusters, GPU and DNN using System-Level IP
Latch-Up 2024: Boston
Massachusetts Institute of Technology 77 Massachusetts Avenue, Boston, MA, United StatesFriday to Sunday April 19–21, 2024 in Boston, MA, USA The Latch-Up conference is a weekend of presentations and networking dedicated to free and open source silicon. It's an event… Read More »Latch-Up 2024: Boston
CICC 2024
DoubleTree by Hilton Denver 3203 Quebec Street, Denver, CO, United StatesThe IEEE Custom Integrated Circuits Conference is a premier conference devoted to IC development. The conference program is a blend of oral presentations, exhibits, panels and forums. The conference sessions… Read More »CICC 2024
IP-SoC Silicon Valley 2024
Hyatt Regency Santa Clara 5101 Great America Parkway, Santa Clara, CA, United StatesA worldwide connected Event !! D&R IP-SoC Silicon Valley 2024 Day is the unique worldwide Spring event fully dedicated to IP (Silicon Intellectual Property) and IP based Electronic Systems. IP-SoC… Read More »IP-SoC Silicon Valley 2024
The Era of Software-Defined Everything: Chiplets and Bespoke Silicon
From fintech to automotive, defense to healthcare, everyone wants bespoke computing platforms to build "software-defined solutions" that are differentiated in their respective markets. Sign up and save your spot for… Read More »The Era of Software-Defined Everything: Chiplets and Bespoke Silicon
TechNES FPGA Front Runner Event
New Mills Wotton-under-Edge, United KingdomThe FPGA Front Runners event will be hosted by Renishaw at their venue in Wotton-under-Edge. The event will focus on “Using AI in development and product for FPGA”. If you… Read More »TechNES FPGA Front Runner Event