Webinar
Addressing Growing Security Challenges with JasperGold
Join Cadence® Training and Product Engineering Architect Joerg Mueller and Senior Application Engineer Tom Weiss for this free technical training webinar. As a chip designer, you’re probably spending as much… Read More »Addressing Growing Security Challenges with JasperGold
Benefits of a Common Methodology for Emulation and Prototyping
Many design teams have used some form of hardware verification throughout their verification cycle for years now. Some engineering teams prefer to use emulation, some prefer to use prototyping, and… Read More »Benefits of a Common Methodology for Emulation and Prototyping
UVM for FPGAs (Part 4): IEEE 1800.2 UVM Updates
Abstract: Started with an early adaptor release as Accellera 1.0a, UVM has evolved into few significant versions including UVM 1.1 and UVM 1.2. As with many popular useful standards, UVM… Read More »UVM for FPGAs (Part 4): IEEE 1800.2 UVM Updates
Effectively Addressing the Challenge of Securing Connected and Autonomous Vehicles
Overview As vehicles get more complex and connected, the attack surface increases. This presents increasing challenges for cybersecurity. This webinar introduces hardware based techniques for addressing security concerns, from legacy… Read More »Effectively Addressing the Challenge of Securing Connected and Autonomous Vehicles