Webinar
Addressing Growing Security Challenges with JasperGold
Join Cadence® Training and Product Engineering Architect Joerg Mueller and Senior Application Engineer Tom Weiss for this free technical training webinar. As a chip designer, you’re probably spending as much… Read More »Addressing Growing Security Challenges with JasperGold
Benefits of a Common Methodology for Emulation and Prototyping
Many design teams have used some form of hardware verification throughout their verification cycle for years now. Some engineering teams prefer to use emulation, some prefer to use prototyping, and… Read More »Benefits of a Common Methodology for Emulation and Prototyping
UVM for FPGAs (Part 4): IEEE 1800.2 UVM Updates
Abstract: Started with an early adaptor release as Accellera 1.0a, UVM has evolved into few significant versions including UVM 1.1 and UVM 1.2. As with many popular useful standards, UVM… Read More »UVM for FPGAs (Part 4): IEEE 1800.2 UVM Updates
Effectively Addressing the Challenge of Securing Connected and Autonomous Vehicles
Overview As vehicles get more complex and connected, the attack surface increases. This presents increasing challenges for cybersecurity. This webinar introduces hardware based techniques for addressing security concerns, from legacy… Read More »Effectively Addressing the Challenge of Securing Connected and Autonomous Vehicles
Entering a New Era with Linux-Based Automotive Software-in-the-Loop Test Tools
Trends such as advanced driver assistance systems (ADAS) and autonomous driving (AD) make software the differentiating factor in the automotive industry. To keep pace with innovations and to shorten development cycles, testing… Read More »Entering a New Era with Linux-Based Automotive Software-in-the-Loop Test Tools
The most error prone FPGA corner cases
Presenter: Espen Tallaksen, CEO of EmLogic Thursday, October 14, 2021 Abstract: Cycle related corner cases are probably the worst and main reason for undetected bugs on many FPGAs. To explain… Read More »The most error prone FPGA corner cases
Defending the Cloud: PCIe and CXL Data Security for High-Performance Computing
Cloud computing is going through a significant overhaul and continues to grow globally with increasing presence of hyperscale cloud providers for big data, high-performance computing (HPC), and analytics. In-house data… Read More »Defending the Cloud: PCIe and CXL Data Security for High-Performance Computing
Advanced Antenna Design and Integration Through Circuit/EM Co-Simulation
The Cadence® AWR® V16 for RF Design Excellence Webinar Series introduces the latest capabilities in Cadence® AWR Design Environment® Version 16 (V16), providing ready access to Cadence Clarity™ 3D Solver… Read More »Advanced Antenna Design and Integration Through Circuit/EM Co-Simulation
Python in Verification Online Meetup
Veriest is inviting you to another event in our series of online Verification Meetups. This time, we'll have two presentations on the polemic topic of using Python in Verification, one… Read More »Python in Verification Online Meetup
Compare Performance-power of Arm Cortex vs RISC-V for AI applications
In the Webinar, we will show you how to construct, simulate, analyze, validate, and optimize an architecture model using pre-built components. We will compare micro and application benchmarks on system… Read More »Compare Performance-power of Arm Cortex vs RISC-V for AI applications
Using OVL for Assertion-based Verification of Verilog and VHDL Designs
Open Verification Library (OVL) is a library of property checkers for digital circuit descriptions written in popular Hardware Description Languages and maintained by Accelera. The OVL checkers could be used… Read More »Using OVL for Assertion-based Verification of Verilog and VHDL Designs
Managing SoC Subsystems and Other Hierarchy With Methodics IPLM
For the past 10+ years, semiconductor design has moved from a project-based "start again" mindset to a more modular, "IP-centric" approach. This has significantly reduced project cost and improved time-to-market… Read More »Managing SoC Subsystems and Other Hierarchy With Methodics IPLM