Webinar
Events
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Ways to run cocotb: makefiles, cocotb-test, or your custom setup
cocotb enables Python-based hardware verification, and it integrates into your simulator of choice, such as Aldec's Riviera-PRO and executes Python testbenches in that context. In this webinar, we will look at ways to invoke your simulator of choice in a way that also starts with cocotb. We will show ways to extend the setup to…
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Elevating Consumer Electronics Design Through Cloud-Based Simulation
Electronics design engineering teams are under incredible pressure to quickly deliver innovative new product designs to meet skyrocketing market demand. Sign up for this webinar to learn more about designing better consumer electronics products thanks to simulation in the cloud. About this Webinar Consumer electronic devices are part of our daily lives and include phones,…
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Tackling Challenges in 3D Heterogenous Integrated (3DHI) Microelectronics for Aerospace, Government, and Defense Systems
Join industry experts from aerospace, government, and defense as they discuss the complexities of 3D Heterogeneous Integration (3DHI), highlighting some of the technological, manufacturing, and economic complexities as well as security, reliability, and safety challenges. The panelists will also share their insights on chiplets and interface compatibility in addition to how DARPA’s NGMM (Next-Generation Microelectronics Manufacturing research…
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PCB Design Best Practices: Design Automation
re you harnessing the full power of your PCB design software? In this live discussion, experts Stephen Chavez and Ray Macias will discuss the benefits of using PCB design automation, and show how certain capabilities such as component placement, trace routing, and generating manufacturing outputs to include intelligent data formats can improve your design cycle times. They’ll offer…
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Automated Constraints Promotion Methodology from IP to SoC for Complex Designs
IP cores require integration into top-level subsystems and/or SoCs. Writing constraints manually for top level design is prone to errors and difficult to verify and manage. This Synopsys webinar will cover how automated SDC constraints promotion from the IP to SoC level provides high-quality SDC using Synopsys Timing Constraints Manager relative to manual time-consuming approaches. We will…
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Leverage Certified RISC-V IP to Craft ASIL ISO 26262 Grade Automotive Chips
As semiconductor industry leaders, Bosch, Infineon, Nordic Semiconductor, NXP, and Qualcomm collaborate to drive the acceleration of automotive RISC-V semiconductors, join us for an insightful webinar on how you too can unlock the full potential of RISC-V within your automotive SoC. Featuring Andes Technology and Green Hills Software, this webinar will offer key insights into…
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Why Chiplets with UCIe are the Next Big Thing
Artificial intelligence (AI) and virtual reality (VR) require fast, efficient, low-power technologies. Transistors are becoming harder and harder to shrink, so chiplets are a promising alternative. Chiplets are small, modular dies that use UCIe, an open industry standard, to communicate with each other. Combined in a Systems-on-Package (SoP), they provide superior performance, reduced power consumption, and increased design flexibility for customized applications…
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Fail-safe Electronics for Automotive
I would like to invite you to attend our upcoming webinar on Wednesday, November 15 at 8 a.m. PST. This 1-hour panel will feature SoC experts from CARIAD, Infineon, NXP and proteanTecs, who bridge both the semiconductor and automotive worlds. The discussion will revolve around "Fail-Safe Electronics for Automotive," a topic of paramount importance in…
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Achieve 95% Accurate Power Measurement during Architectural Exploration
Are you in the conceptualization and architectural exploration phases, where assessing the power budget is of paramount importance? If you're looking to achieve precise power measurement for critical aspects like embedded software, power management algorithms, hardware configurations, and more, this webinar is tailor-made for you. Webinar: How to achieve 95%+ Accurate Power Measurement during…
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ASIP University Day 2023
ASIP University Day: Domain-Specific Processor Design using ASIP Designer Application-specific instruction set processors (ASIPs) have established themselves as an important implementation option for modern SoCs, i.e. when standard processor IP cannot meet challenging application-specific requirements, and fixed hardware is not flexible enough. Heterogeneous multicore systems including ASIPs are now becoming more mainstream. Domains such as…
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ParagonX – Intelligent analysis, visualization and debugging tool for IC layout parasitics
I would like to invite you to Ansys Paragon X webinar that we are hosting on Wednesday, November 15th 17:00 PM (Israel time). ParagonX intended for analyzing, simulating, debugging, visualizing, and improving IC layout parasitics. It helps analog designers and layout engineers to immediately understand the parasitics and allows to reduce parasitics debugging time from…
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Boost SoC debug and analytics with embedded software and smart monitors
On-chip monitors and debug structures can dramatically simplify debug, validation, analytics, and optimization of complex SoCs. Such monitors are often accessed by software executing on an external host or debugger via USB or JTAG. In this webinar, we will demonstrate how embedded software running on the target silicon for many use cases provides a superior alternative…