Webinar
Events
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Proactively Address Thermal Concerns in Advanced IC Packages
The heterogeneous integration of chips and chiplets in IC packages is all the rage as we face “More than Moore” performance challenges. While these innovative design practices successfully address performance goals, some design teams find that IC packages may overheat if they do not carefully plan for heat dissipation. This webinar will show how design…
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The UCIe™ 1.1 Specification: Future Applications of Chiplets
Presenter: Dr. Debendra Das Sharma, UCIe Consortium Chairman and Intel Senior Fellow, Chief Architect of I/O Technology and Standards at Intel The UCIe™ (Universal Chiplet Interconnect Express™) 1.1 Specification was released in August 2023, delivering valuable improvements to the chiplet ecosystem, extending reliability mechanisms to more protocols and supporting broader usage models. This webinar will provide…
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DVClub Europe – AI/ML in Verification
This is to inform you that the next DVClub Europe meeting takes place on Tuesday 17th October with a theme of "AI/ML in Verification". This DVClub consider how we can save time and effort whilst improving time-to-market through the application of AI/ML to verification. Agenda (BST) 12:00 Welcome and Introduction - Mike Bartley, Senior Vice President -…
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Soar to New Heights of Productivity using Cadence Managed Cloud Services
Date: Wednesday, October 18, 2023 Time: 8:30am PT | 10:30am CT | 11:30am ET Join us for this 45-minute webinar to learn how the Cadence-managed, EDA-optimized, ready-to-use, and secure ISO-certified cloud platform delivers a fully integrated and proven environment to jump-start product design, verification, and implementation. See the platform in action as we demo the productivity features…
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System-Level Thermal Signoff from Chips Through to Racks
Today’s modern electronic designs require ever more functionality and performance to meet consumer demand. These challenges become more critical and complex when resistive losses in PCB and package structures are significant since resistive losses are temperature dependent. In this webinar, we will look at an electrothermal co-simulation solution for the full hierarchy of electronic systems…
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High Reliability and Functional Safety Applications for FPGA
When designing any new system, safety and reliability are key factors in determining if a system is safe for real-world deployment and if there are sufficient contingency plans for worst case scenarios. This is no different for the designs targeted for FPGAs based deployments. Today, FPGA based designs are utilized in many safety critical systems in the…
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Enhance Verification Quality with the Xcelium Mixed-Signal App
The comprehensive verification of analog mixed-signal (AMS) designs has challenges in schedules and implementations due to the vast divergence in design flows of the analog and digital portions of the SoC. These discrepancies include priorities in simulation cycles (accuracy versus performance), design methodologies, and verification of functionality. Over multiple decades, design verification (DV) has evolved…
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Mastering the Art of Managing IP, Chiplets, and Design Data
Join us on Wednesday, November 1st, for an eye-opening exploration of the inadequacy of common design data and IP management capabilities in the face of today’s intricate semiconductor chip designs. Discover the keys to unlocking unparalleled success in your upcoming designs through cutting-edge capabilities and strategies that are reshaping the industry. Don’t miss this exclusive opportunity…
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Warp Speed Gate-Level Simulations with the Xcelium Multi-Core App
Are you ready to lead the way in gate-level digital simulations (GLS)? Dive into Cadence’s exclusive webinar and uncover the revolutionary Xcelium Multi-Core (MC) App—a game changer for GLS, allowing you to parallelize and expedite simulations like never before. What You'll Gain: Insight: Understand why the Xcelium MC App is crucial for DV engineers looking…
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Proactive Data Center Management with Insight Platform
The DataCenter Insight Platform is an enterprise software solution that simplifies data center capacity management by making it proactive, rather than reactive. The platform is a database of data center “digital twins”—virtual models reflecting the aggregate of an organization’s toolsets and add/move/change workflows. By bringing together data that is typically siloed and using predictive computational…
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Deep Dive into the UVM Register Layer: User-Defined Doors, Predictors, and Callbacks
This webinar focuses on three specific aspects of the UVM register layer that will help you to model in UVM some of the less obvious ways in which registers can behave, such as non-linear addressing, burst access mode, registers accessed through an embedded CPU, and quirky registers. It will cover the following topics: Using user-defined…
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CMOS Circuit Techniques for Wireline Transmitters Part I
Synopsys Webinar – Part I In this 3-part Synopsys webinar series, we will present how hyperscale data centers are going through a paradigm shift with the advent of technologies like Artificial Intelligence (AI) and edge compute requiring hyperscale data centers to support exponential growth of data volume. This volume of network traffic demands an increase…