Webinar
Events
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QuantumATK V-2023.09 Release: Highlights of New and Enhanced Features
Join our FREE online event to learn about the new and enhanced features and performance improvements in the latest QuantumATK V-2023.09 product release. - Enhanced ease-of-use of training Machine-Learned FFs with new predefined Workflow Builder blocks and templates - New interactive Interfaces Builder for building multilayer structures - New Accelerated molecular dynamics method for crystallization…
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Efficient Bluespec RISC-V Processor Verification for Highest Coverage Closure: A Comprehensive Case Study
The ability to mix and match multiple ISA extensions and add user-defined ISA extensions makes RISC-V verification more challenging than conventional processor verification. This Synopsys webinar demonstrates the verification of standard RISC-V ISA extensions. A subsequent webcast will demonstrate custom ISA verification. The multiple ISA verification problem is solved by RISCV-DV with configurability for ISA…
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UCIe-Based Chiplet Verification – from IP to SoC
Innovative die disaggregation technologies, enable a future where a catalog of chiplets will be available to mix and match based on the end application. The industry’s fastest emerging interconnect standard called Universal Chiplet Interconnect Express (UCIe) enables end users to combine chiplets with different functionality and technology nodes to develop highly sophisticated electronic chips. Hence,…
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Applications of Formal Verification
It is an exciting time to explore a career in the VLSI semiconductor sector, and we're here to help you gain clarity on buzz and provide information on educational options towards a successful entry to this field with long-term career prospects. Design Verification is one of the essential and most promising career options. In the…
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Unleashing Innovation with UCIe
Exploring the Next Frontier in Chip Integration Webinar Agenda : Introduction to all UCIe layers Decrypting FLITs, PHY Trainings, Bring up flows FDI-RDI , main band and side band FLIT transfers etc. Implementation of Stacks-Arbiter, Retry mechanism & Retimer implementations Showcasing UCie FLIT transfer flow between multidies Enhancements done in UCIe 1.1 Who Should Attend:…
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Synopsys VSO.ai Virtual Workshop
Virtual workshop with hands-on labs Achieving coverage closure continues to remain a challenge for customers and there is a growing need for a system to work autonomously to reach the target as quickly and cheaply as possible with the highest quality of results. The recently released Synopsys VSO.ai address this challenge in addition to inferring…
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Cadence Training: Cerebrus Intelligent Chip Explorer
Please join me, Cadence Training and Application Engineer Krishna Atreya, for this free technical Training Webinar. What Is the Webinar About? The Cadence Cerebrus Intelligent Chip Explorer is a revolutionary, machine learning-driven, automated approach to chip design flow optimization. Block engineers specify the design goals, and Cadence Cerebrus intelligently optimizes the Cadence digital full flow…
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Stratus HLS Automated Power Shutoff to Minimize Power and Retention Registers
Power Shutoff is a popular technique for saving power during functionally idle periods. Implementing Power Shutoff requires a detailed understanding of which resisters must be retained to enable bring-up from the power-off state. Identifying the minimal set of retention registers is challenging and grows more difficult with design complexity. This CadenceTECHTALK introduces a novel High-Level…
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FPGA Design Verification – Advanced Testbench Implementation
Abstract As FPGA technology continues to evolve - to provide us with full-blown SoCs with CPU, GPU, and high-speed peripherals, for example, joining the traditional programmable logic area - design verification becomes increasingly challenging. Lab-based FPGA testing and bring-up alone are clearly insufficient, especially for safety-critical designs, and FPGA teams are adopting advanced design verification…
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Verisium Debug for UVM Testbench
Verisium Debug offers comprehensive debugging capabilities. From RTL and UVM testbench to UPF low-power designs, Cadence’s unified debugging platform helps users debug. In this webinar, users will learn about the available features in Verisium Debug for UVM testbench and use these unique capabilities to visualize and debug the UVM testbench. What you will learn Understand…
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FPGA Design Verification – Advanced Methods
Abstract As FPGA technology continues to evolve - to provide us with full-blown SoCs with CPU, GPU, and high-speed peripherals, for example, joining the traditional programmable logic area - design verification becomes increasingly challenging. Lab-based FPGA testing and bring-up alone are clearly insufficient, especially for safety-critical designs, and FPGA teams are adopting advanced design verification…
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Mapping signal processing algorithms on AMD-Xilinx Versal to meet timing and power constraints
In this Webinar, we will focus on the performance-power-area trade-off in implementing signal processing algorithms on Xilinx FPGA by partitioning the tasks of the algorithms onto the processors, logic and AI Engines resident in the AMD-Xilinx Versal FPGA. Key Takeaways: Discover the inner workings of FPGA components: Processor, Logic Elements, AIE/Tensor, and more. Understand latency…