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ITherm 2022
Sheraton Hotel & Marina 1380 Harbor Island Drive, San Diego, CA, United StatesWelcome to ITherm 2022 The Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems May 31 - June 3, 2022 Sheraton Hotel & Marina San Diego, CA USA (Co-Located with ECTC) Sponsored by the IEEE's Electronics Packaging Society (EPS), ITherm 2022 is an international conference for scientific and engineering exploration of thermal, thermomechanical and emerging… ITherm 2022
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Automotive Ethernet Congress
Hilton Munich Airport Terminalstraße Mitte 20, 85356 München-Flughafen, Munich, GermanyWELCOME POWERFUL NETWORK FOR THE COMPUTER ON WHEELS The Automotive Ethernet Congress will take place for the eighth time on June 1 - 2, 2022. The conference program will highlight the entire spectrum of topics relating to the use of Ethernet in vehicles. The vehicle is undergoing the greatest change since its inception. Automation, networking, and digitalization of the… Automotive Ethernet Congress
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Become an SVA Expert in One Hour
Doulos Co-Founder & Technical Fellow John Aynsley will teach the core principles necessary to understand and use SystemVerilog Assertions, focussing on the aspects of SVA that are applicable to both formal verification and simulation. Particular emphasis will be placed on the core semantics of temporal logic so that you will be able to write your own assertions,… Become an SVA Expert in One Hour
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ASYNC 2022 Summer School: Behavioral Design
The steering committee of the IEEE ASYNC symposium is organizing a summer school on asynchronous design. The goal of the school is to teach asynchronous chip design to students and practitioners interested in digital hardware design. Participants will learn how to design asynchronous circuits at the behavioral level, gate level, and physical design level using… ASYNC 2022 Summer School: Behavioral Design
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Embedded Applications Get a Helping Hand: Extensible Processor Architectures
Industry consolidation and cost streamlining eliminated many proprietary processor architectures and channeled alignment to a subset of standardized instruction set architectures (ISAs). Today, many embedded applications such as those found in artificial intelligence (AI), automotive and storage segments require increased bandwidth and memory address space expansion. As Moore’s law slows, design teams seek different ways… Embedded Applications Get a Helping Hand: Extensible Processor Architectures
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Customers Discuss Their Real World Use of High-Level Synthesis
Summary The focus of this seminar is to have real-world customers present their successes using Catapult High-Level Synthesis (HLS) in markets such as Automotive, 5G/Communications, Video/Imaging, AI/ML, and MEMs Sensors. The companies who will be presenting are: Google (Video/Imaging) NASA-JPL (Video/Imaging) NVIDIA (Video/Imaging) NVIDIA Research (AI/ML) NXP Semiconductors (Automotive) STMicroelectronics (MEMS Sensors) Viosoft (5G/Communications) In… Customers Discuss Their Real World Use of High-Level Synthesis
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CadenceLIVE 2022 – Silicon Valley
Cadence San Jose, CA, United StatesAre you driving design change or feel you’ve overcome challenges that could impact the electronic revolution? CadenceLIVE™ offers you an opportunity to tell your story. Showcase your expertise and offer tips to address the complexities and challenges that engineers face today. CadenceLIVE Silicon Valley features peer presentations that highlight solutions, using Cadence® products, for today’s… CadenceLIVE 2022 – Silicon Valley
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From Virtual ECU to Real Vehicle: Continuous Testing of Functional Requirements
Today, most of the software functions in a car can be tested efficiently using virtual ECU models and DevOps engineering methods. However, final acceptance tests with real vehicles are still mandatory, even though they are expensive and time-consuming. The prevalent problem is the gap between automated virtual methods and manual testing, which further increases costs… From Virtual ECU to Real Vehicle: Continuous Testing of Functional Requirements
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How to Eliminate Image Retention Issues with SmartSpice Flex Modeling
Image retention is a long-standing issue in the display community. To effectively solve this issue, or even to minimize its impact on their products, display manufacturers and consumer electronics vendors need to simulate this effect at the SPICE level. However, image retention is a result of dynamic device effects that cannot be modeled by other… How to Eliminate Image Retention Issues with SmartSpice Flex Modeling
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5X Faster Equivalence Checking with Formality ML-driven DPX
Synopsys’ Fusion Compiler provides a broad spectrum of aggressive optimization techniques such as retiming, multibit banking and advanced data-path optimization that our designers want to take advantage of to achieve maximum PPA. Our expectation from production quality Equivalence checking is to be able to complete verification with minimal efforts and the fastest turn-around-time. This presentation… 5X Faster Equivalence Checking with Formality ML-driven DPX
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Better FPGA Verification with VHDL – Faster than “Lite” Verification Component Development with OSVVM
Some methodologies (or frameworks) are so complex that you need a script to create the initial starting point for writing verification components, test cases, and/or the test harness. SystemVerilog + UVM is certainly like this. There are even several organizations that propose that you use their "Lite" or "Easy" approach. Creating a verification component (VC)… Better FPGA Verification with VHDL – Faster than “Lite” Verification Component Development with OSVVM
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ASYNC 2022 Summer School: Gate-level Design
The steering committee of the IEEE ASYNC symposium is organizing a summer school on asynchronous design. The goal of the school is to teach asynchronous chip design to students and practitioners interested in digital hardware design. Participants will learn how to design asynchronous circuits at the behavioral level, gate level, and physical design level using… ASYNC 2022 Summer School: Gate-level Design
12 events found.